Adaptive equalization using correlation of edge samples with...

Pulse or digital communications – Equalizers – Automatic

Reexamination Certificate

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Reexamination Certificate

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07639737

ABSTRACT:
An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

REFERENCES:
patent: 6734920 (2004-05-01), Ghosh et al.
patent: 7508872 (2009-03-01), Yamazaki
Brunn, Brian et al., “Edge-Equalization Extends Performance in Multi-Gigabit Serial Links.” DesignCon 2005. 13 pages.
Abramovitch, Danny “Lyapunov Redesign of Classical Digital Phase-Lock Loops.” Communications and Optics Research Lab, Agilent Technologies. 22 pages. Jun. 5, 2003.
Abramovitch, Danny “Phase-Locked Loops: A Control Centric Tutorial.” Communications and Optics Research Lab, Agilent Technologies. 50 pages. May 8, 2002.

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