Adaptive DRAM timing set according to sum of capacitance valves

Details Adaptive DRAM timing set according to sum of capacitance valves Adaptive DRAM timing set according to sum of capacitance valves

1994-11-29

1996-04-02

Robertson, David L.

395494, 395700, G06F 104

Patent

active

055048773

ABSTRACT:
Timing is set for DRAM memory access in a computer by polling the DRAM memory banks, calculating capacitive load by accessing a prestored table of capacitive load versus DRAM size, and assigning wait states according to calculated capacitive load by accessing a prestored formula. In one embodiment, wait states are assigned in increasing increments for increasing total capacitive load. In an alternative embodiment, timing is assigned bank by bank. Control routines are preferably a part of a system BIOS.

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