Adaptive digital filter architecture for parallel output/update

Details Adaptive digital filter architecture for parallel output/update Adaptive digital filter architecture for parallel output/update

1992-11-19

1994-01-25

Nguyen, Long T.

Boots, shoes, and leggings

G06F 1531

Patent

active

052821552

ABSTRACT:
The disclosed adaptive finite impulse response (FIR) digital filter architecture computes tap coefficient updates in parallel with and simultaneously with the computation of the filter output at each iteration. The filter includes a filter output processor (206) and a tap update processor (212) which respectively process, in parallel, the filter output and the coefficient updates for a subsequent iteration. The filter output processor and the tap update processor form their respective outputs at each iteration from input signal values at previous iterations stored in a filter input memory (203) and from tap coefficients stored in a filter taps memory (205). In even-numbered iterations only the even-numbered taps are updated and in odd-numbered iterations only the odd-numbered taps are updated. At every iteration, in forming the filter output and the even or odd tap updates, the previous inputs and tap coefficients are accessed in a pattern that requires that they be fetched only once from their respective memories.

REFERENCES:
patent: 4792915 (1988-12-01), Adams et al.
B. A. Mordecai, T. R. Hsing, D. L. Waring and D. S. Wilson "Repeaterless Technology Brings Copper and Fiber Together," Telephony, Jul. 2, 1990, pp. 28-33.
R. D. Gitlin, et al., "The Tap-Leakage Algorithm: An Algorithm for the Stable Operation of a Digitally . . . , " Bell Syst. Tech. J., vol. 61, pp. 1817-1839, 1982.
G. Long, et al., "The LMS Algorithm with Delayed Coefficient Adaptation," IEEE Trans. on ASSP vol. 37, pp. 1397-1405, 1989.

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