Adaptive digital filter

Details Adaptive digital filter Adaptive digital filter

2000-03-16

2004-06-01

Ngo, Chuong Dinh (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06745218

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an adaptive digital filter circuit for performing a coefficient adaptation operation by adaptively updating the filter coefficient.
2. Description of the Related Art
A digital filter is a filter for performing a predetermined operation on input signals (input data) which are discrete from each other along the time axis and along the amplitude axis so as to output signals (filtered data) which are also discrete along the time axls and along the amplitude axis.
Among various digital filters, those in which the parameter for the predetermined operation is not fixed but varies over time such that intended output signals are obtained are called “adaptive digital filters”, and such an intended output signal is called a “reference signal”.
For example, an adaptive digital filter may be used for waveform equalization performed in a read/write channel LSI which is used in HDD (hard disk drive). In recent years, there is a demand for increasing the data transmission rate of digital devices such as HDD. Accordingly, there is a demand for increasing the operation speed of an adaptive digital filter circuit for performing the adaptive digital filtering process. Moreover, as portable personal computers become widespread. there is also a demand for reducing the size and power consumption of an adaptive digital filter circuit.
An adaptive digital filter circuit can be functionally divided into a filtering circuit and an adaptation circuit. The filtering circuit is a circuit for performing an operation using predetermined input data xi and coefficient data ai so as to obtain filtered data y′ and filter output data y. The adaptation circuit is a circuit for performing a coefficlent adaptation operation, i.e., adaptively updating the coefficient data ci so that the output of the filtering circuit, i.e., the filtered data y′, converges to an intended reference value Y.
The configuration and the operation of a conventional adaptive digital filter circuit will now be described with reference to the accompanying drawings.
FIG. 12
illustrates the configuration of the conventional adaptive digital filter circuit.
The adaptive digital filter circuit includes a pipelined filtering circuit
100
and a pipelined adaptation circuit
500
. The pipelined filtering circuit
100
corresponds to the filtering circuit as described above. Specifically, the pipelined filtering circuit
100
performs an operation using the predetermined input data xi and coefficient data ci (i is an integer satisfying 1≦i≦n) so as to obtain the filtered data y′, The pipelined adaptation circuit
500
corresponds to the adaptation circuit as described above. Specifically, the pipelined adaptation circuit
500
adaptively updates the coefficlent data ci so that the output of the filtering circuit, i.e., the filtered data y′, converges to the intended reference value Y.
For each of the pipelined filtering circuit
100
and the pipelined adaptation circuit
500
of the conventional adaptive digital filter circuit, the entire operation process is performed in a pipelined process. This is because a pipelined process is most suitable for realizing the recent demand in the art, i.e., the increase in the operation speed of an adaptive digital filter circuit.
The term “pipelined process” as used herein refers to a process of successively receiving and processing a plurality of input signals to successively output the operation results, in which an input signal is received before outputting the operation result of a preceding input signal. Each input signal is processed through a plurality of stages provided in the circuit which are independent from one another, in which each stage processes the input signal and then passes the processed signal to the next stage.
The pipelined filtering circuit
100
receives the input data xi (i is an integer satisfying 1≦i≦n), the coefficient data ci (i is an integer satisfying 1≦i≦n) and a primary clock signal clk having a cyole of T. The pipelined filtering circuit
100
performs a predetermined operation using the received input data xi and the coefficient data cti so as to output the filtered data y′. The filtered data y′ is input to the pipelined adaptation circuit
500
. The pipelined filtering circuit
100
performs a pipelined process based on the primary clock signal clk.
FIG. 12
shows the filtered data y′ and the filter output data y as the outputs of the pipelined filtering circuit
100
. The relationship between the filtered data y′ and the filter output data y is as follows. The filtered data y′ is the result of the predetermined operation as described above, and the filter output data y is a signal obtained by latching the filtered data y′ in response to the primary clock signal clk so as to adjust its timing before it is output to a subsequent circuit, e.g., a Viterbi decoding signal circuit in a read/write channel (R/W ch) LSI. The filtered data y′ before the latching process is used as the input to the pipelined adaptation circuit
500
so that it is possible to omit latching processes using registers and to avoid an unnecessary delay, thereby reducing the number of stages of the entire adaptive digital filter circuit and increasing the speed of the coefficient data update process.
The pipelined adaptation circuit
500
receives the input data xi (i is an integer satisfying 1≦i≦n), the output from the pipelined filtering circuit
100
, i.e., the filtered data y′, the primary clock signal clk, and the secondary clock signal clkc. The pipelined adaptation circuit
500
adaptively updates the coefficient data ci so that the output of the pipelined filtering circuit
100
, i.e., the filtered data y′, converges to the intended reference value Y. The pipelined adaptation circuit
500
performs a pipelined process based on the primary clock signal clk. In other words, in the pipelined filtering circuit
100
and in the pipelined adaptation circuit
500
, data is passed from one stage to another in synchronization with the cycle of the primary clock signal clk. The pipelined adaptation circuit
500
uses the secondary clock signal clkc for latching the updated coeff icient data ci to be output later in a register. As will be more fully discussed below, the secondary clock signal clkc used for latching the coefficient data ci in a register is frequency-divided by the latency of the coefficient adaptation operation.
The operation of the adaptive digital filter circuit will now be described by describing each of the operation performed by the pipelined filtering circuit
100
and the operation performed by the pipelined adaptation circuit
500
.
A commonly-employed adaptive digital filter circuit performs an operation based on an algorithm called “LMS (least mean square)”.
For any natural number
1
, the input data xi (i is an integer satisfying 1≦i≦n) has a relationship represented by Expression 1 below.
x
1
[0
]=x
2
[
T]= . . . =xn
[(
n
−1)
T]
  Expression 1
Herein, x
2
[T], for example, denotes input data x
2
which is input at time t=T. T denotes the cycle of the primary clock signal clk.
The pipelined filtering circuit
100
receives the coefficient data ci (i is an integer satisfying 1≦i≦n) which is output from the pipelined adaptation circuit
500
. The initial value of the coefficient data ci at the beginning of an operation may be a coefficient value which has been previously stored in the pipelined filtering circuit
100
or a coefficient value which has been previously stored in the pipelined adaptation circuit
500
and output to the pipelined filtering circuit
100
.
The pipelined filtering circuit
100
caloulates the filtered data y′ according to Expression 2 below by using the input data xi and the coefficient data ci.
 
y′=&Sgr;ci·xi
  Expression 2
Upon receiving the

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