Adaptive digital filter

Multiplex communications – Wide area network – Packet switching

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355 14, 364724, 379411, H04J 1500, H03H 730, G06F 738

Patent

active

046944516

ABSTRACT:
A digital filter comprises a plurality of delay stages 41 such as shift register stages through which an input x(t) is fed. Each of a plurality of individually addressable random access memories 42 is addressed by the output of one of the delay stages and the output from the RAMs 42 are combined. An error signal adapts the values stored within the RAMs. The filter may also be extended such that each RAM receives an address input from more than one delay stage.

REFERENCES:
patent: 3777130 (1973-12-01), Croisier et al.
patent: 4146931 (1979-03-01), Delforge
patent: 4435823 (1984-03-01), Davis et al.
"A Digital Transmission Unit for the Local Network", by P. J. Van Gerwen et al, Conference on Communications Equipment and Systems, pp. 65-69, 20-22 Apr. 1982.
"Versatile Digital Arithmetic Unit with Rams", by M. A. Bin Nun, Electronic Engineering, vol. 48, No. 580, pp. 18-19, Jun. 1976.

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