Adaptive digital clock recovery

Details Adaptive digital clock recovery Adaptive digital clock recovery

1998-05-01

2001-06-26

Jung, Min (Department: 2663)

Multiplex communications

Data flow congestion prevention or control

Flow control of data transmission through a network

C370S356000, C370S516000, C375S371000

Reexamination Certificate

active

06252850

ABSTRACT:

The invention relates to a method and apparatus for digital clock recovery, in particular for a packet oriented network environment.
An example of a packet oriented transmission technology for the realization of Broadband Integrated Service Networks (BISDN) is the technology called Asynchronous Transfer Mode (ATM). This permits services as diverse as voice, data and video to be transmitted through the same medium and in the same format. The transport of constant bit rate (CBR) data over an ATM network is usually referred to as circuit emulation. The accommodation of constant bit rate (CBR) services by ATM is particularly important, for compatibility with existing systems and future networks, even if ATM is more suitable to the transport of bursty traffic, such as data. One of the critical issues of circuit emulation is the recovery of clock frequency of the source data (the service clock frequency) at the receiver.
ATM's basic transport entity is a 53 byte cell. Five of these bytes are header bytes, and convey information such as link-to-link routing, error correction, service information (priority, payload identifier), and cell type identification. A protocol stack is defined by ITU-T for ATM technology, in which the so-called ATM layer performs operations typically found in layers
2
and
3
of the OSI model. Above the ATM layer is an ATM adaptation layer (AAL), which is divided into segmentation and reassembling layers (SAR) and a convergence sublayer (CS). Five different types of AAL have been defined by ITU-T, covering various applications. The AAL-
1
(ATM Adaptation Layer
1
) is devoted to CBR services. Of the 48 remaining information bytes of an ATM cell, one used by the AAL
1
SAR for functions including timing recovery and cell loss detection which leaves 47 data bytes (376 bits). To transport a CBR service into an ATM network, the data is segmented into cells of 47 bytes, an SAR byte is then added to each cell, the 48 bytes are mapped in an ATM cell and are then sent through the network.
As a result of statistical multiplexing of cells at the source and of queuing delays incurred in ATM switches, successive cells arrive to the destination a periodically. The deviation from ideal arrival time is called cell jitter or cell delay variation (CDV). It obviously increases with the network load, as queuing delays are functions of the switch load. Cell jitter is composed of a relatively high frequency stuffing jitter and of a low frequency waiting time jitter. The problem with cell jitter is that it can be very large, and except for the fact that its average is zero, its characteristics are mostly unknown.
The ITU-T has set output clock jitter recommendations whereby the frequency shift at 2.048 MHz on service clocks is +/−50 ppm (1 ppm=1 part per million=2.048 Hz shift).
In order to achieve clock recovery, the exact source frequency should be recovered at the receiver. However, this is not straightforward due to the problems of output jitter and wander control. Jitter is defined as the higher frequency characteristics of a phase variation on a given clock signal. Wander is the lower frequency part of this phase variation. Both are commonly measured in terms of unit intervals (UI), where one UI corresponds to one cycle of the clock signal. ITU-T recommendation G.823 has precisely defined output jitter limits that must be met if the system is to be compatible with any CBR equipment. The bounds on maximum peak-to-peak output jitter for 2.048 Mbits.s
−1
CBR services are shown in Table 1.
TABLE 1
Frequency
20 Hz-18 kHz
18 kHz-100 kHz
Jitter
1.5 UI
0.2 UI
Wander tolerance is not as well defined as output jitter. However, input jitter should not be greater than 36.9 UI under 1.2×10
−5
Hz.
Two methods exist for the recovery of the service clock at a receiver. A first method is referred to as the “synchronous method” and is based on the availability of a common network reference clock between the source and the receiver end equipment. This network clock is distributed by the network, and is available either through the Synchronous Digital Hierarchy (SDH) network or its North American version Synchronous Optical NETwork (SONET).
As not all CBR equipment is able or willing to synchronize on this network clock, a second method referred to as the “adaptive method” recovers the service clock based on the fill-level of an incoming cell buffer.
FIG. 1
of the accompanying drawings illustrates a conventional adaptive clock recovery mechanism
10
formed from a cell buffer
12
, a filter
14
and a digitally controlled oscillator
16
, responsive to an output of the filter
14
. As the arrival time of the ATM cells is used to recover the reception clock in the mechanism of
FIG. 1
, this leads to a new problem, as depicted in the
FIGS. 2A and 2B
. As shown in
FIG. 2A
, the output frequency fout is too slow. In
FIG. 2B
, the output frequency fout is still too slow, but cell jitter has appeared. As a result cell jitter must be filtered to get a reasonable accuracy. If it is desired accurately to recover the service frequency, the underlying trend in filter fill level evolution must be determined, by filtering the cell jitter. Given that the permissible range for the service clock is very low, (between +/− 50 ppm at 2.048 MHz) and that cell jitter can be very high (Bellcore proposed a 750 ms delay, that is to say four cells, but this cell jitter can be much higher), the result is that noise which can be 10 times higher than our signal needs to be filtered.
Accordingly, there is a need for an improved adaptive technique for recovery of a service clock.
In accordance with a first aspect of the invention, there is provided an adaptive clock recovery mechanism for an ATM receiver for recovering a service clock transmitted via an ATM network, the mechanism comprising: a first buffer having an input for receiving successive ATM cells from the ATM network and an output; a first buffer fill level controller connected to the first buffer for controlling rates of cell output from the first buffer to be within a predetermined range; a second buffer having an input connected to receive cells from the output of the first buffer and an output; and a second buffer fill level controller connected to the second buffer to cause a rate of cell output from the second buffer to be locked substantially to the service clock frequency.
The adaptive clock recovery mechanism enables the clock of a constant bit rate (CBR) service to be recovered at an ATM receiver where the service is being emulated from an ATM transmitter.
The provision of the first buffer and the first buffer fill level controller enables cell jitter to be filtered prior to recovery of the service clock. An embodiment of the invention can provide adaptive, digital recovery of the service clock at a receiver in a manner which filters the cell jitter and recovers the service clock with acceptable clock jitter.
Preferably, wherein the first buffer fill level controller comprises a selectable clock source for supplying a selectable one of at least a first and a second clock frequency for outputting cells from the first buffer, the selectable clock source being responsive to a fill level of the first buffer to select a clock frequency.
The use of first and second clock frequencies dependent on the fill level of the first buffer provides a simple control structure for keeping the rate of output of cells from the first buffer within a predetermined range. The first buffer with its fill level control thus acts as a low pass filter to reduce high frequency cell jitter.
In a preferred embodiment the first clock frequency has a frequency of from+j ppm and the second clock frequency has a frequency of from−j ppm, where fnom is a nominal service clock and 2j defines the predetermined range. The selectable clock source selects the first clock frequency when a fill level of the first buffer is greater than a threshold value and selects the second clock when a fill level of the first buffer

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