Adaptive differential ADC architecture

Details Adaptive differential ADC architecture Adaptive differential ADC architecture

1999-04-13

2001-05-08

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S155000

Reexamination Certificate

active

06229469

ABSTRACT:

FIELD OF THE INVENTION
This invention is related to electronics and more particularly to an analog-to-digital converter (ADC) architecture for differential signals.
BACKGROUND
The number of bits available for the ADC architecture is limited by speed and power constraints, and currently, for example, for an ADC sampling at 125 MHz, the resolution is limited to 7 bits. The 100-Mbit Ethernet standard calls for at least 7 bits. To illustrate an example of the impact of this limited ADC resolution upon receive channel performance, a 2V peak-to-peak differential signal at a transmitter attenuates to a pulse response of only 185 mV in amplitude (differential) after travelling 150 meters of the 100-Mbit Ethernet cable. Since the ADC architecture must be able to handle a full signal range, which may extend from about 120 mV to the full 2V peak-to-peak with a long sequence of ones, the ADC architecture must allocate available bits to the full range. For example, a 6-bit ADC has only a few bits to quantize a pulse response as small as 120 mV in the above full signal range.
SUMMARY OF THE INVENTION
In order to solve the above and other problems, according to a first aspect of the invention, a method of adaptively converting an analog signal to a digital signal, includes the steps of: generating an analog differential signal based upon a difference between an estimated last sampled signal and a current signal; amplifying the analog differential signal based upon a gain optimized so as to increase the use of a predetermined input range of an analog-to-digital (A/D) converter; converting the amplified analog differential signal to a digital signal in a first number of bits using the A/D converter; and converting the digital signal into an updated estimated last sampled signal according to a second number of bits using a D/A converter, the second number of bits being different from the first number of bits.
According to a second aspect of the invention, a system for adaptively converting an analog signal to a digital signal, includes: a differential signal unit configured to generate an analog differential signal based upon on a difference between an estimated last sampled signal and a current signal; a track-and-hold unit connected to the differential signal unit and configured to track and hold the analog differential signal; an amplifier connected to the track-and-hold unit and configured to amplify the analog differential signal by a gain so as to generate an amplified analog differential signal; a gain optimization unit connected to the amplifier and configured to optimize a gain based upon the analog differential signal, the optimized gain being applied to the analog differential signal so as to increase the use of a predetermined input range; an analog-to-digital converter connected to the amplifier and having the predetermined input range and configured to convert the amplified analog differential signal to a digital signal represented by a first number of bits; an integrator connected to the analog-to-digital converter and configured to integrate the digital signal to generate a current digital signal represented by a second number of bits different from the first number of bits; and a digital-to-analog converter connected to the integrator and configured to convert the current digital signal into an updated estimated last sampled signal according to a second number of bits and based upon the gain.
According to a third aspect of the invention, An integrated circuit having an analog-to-digital converter (ADC) architecture, the ADC architecture includes: a differential signal unit configured to generate an analog differential signal based upon on a difference between an estimated last sampled signal and a current signal; a track-and-hold unit connected to the differential signal unit and configured to track and hold the analog differential signal; an amplifier connected to the track-and-hold unit and configured to amplify the analog differential signal by a gain so as to generate an amplified analog differential signal; an analog-to-digital (A/D) converter connected to the amplifier and having a predetermined input range for converting the amplified analog differential signal to a digital signal represented by a first number of bits; a gain optimization unit connected to the amplifier and configured to optimize the gain based upon the amplified analog differential signal so as to increase the use of the predetermined input range of the A/D converter; an integrator connected to the A/D converter for integrating the digital signal to generate a current digital signal represented by a second number of bits different from the first number of bits; and a digital-to-analog (D/A) converter connected to the integrator for converting the current digital signal into an updated estimated last sampled signal according to a second number of bits and based upon the gain.


REFERENCES:
patent: 3882488 (1975-05-01), Kosakowski et al.
patent: 4590458 (1986-05-01), Evans et al.
patent: 4924224 (1990-05-01), Takahashi et al.
patent: 6100834 (2000-08-01), Lewyn

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