Adaptive decision level circuit

Details Adaptive decision level circuit Adaptive decision level circuit

1980-03-07

1982-04-20

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307359, 328164, 328167, H03K 508, H03K 522

Patent

active

043261698

ABSTRACT:
The adaptive decision level circuit (FIG. 3) slices a digital signal with respect to a decision level disposed between the signal levels. A correction signal generated from the sliced signals (S, S) compensates for variations in the signal levels by maintaining the decision level at a constant position relative to the signal levels. The correction signal is generated by comparing (321) the integrated difference (on lead 305) between the sliced signal and its complement with the statistically expected value (312) of the difference between the sliced signal and its complement. In the preferred embodiment, the expected value is equal to one-half the signal swing of the sliced signal.

REFERENCES:
patent: 3534273 (1970-10-01), Thomas
patent: 4263555 (1981-04-01), Hunka
M. A. Byington et al., Design and Performance of A 16-State Digital Modem ICC Conference Record, vol. 1, 1979 pp. 5.4.1-5.4.6.
M. Washio et al., 1.6 Gbls 16-Level Superposed APSK Modem with Baseband Signal Processing Coherent Demodulator, IEEE MTT-S International Microwave Symposium, vol MTT-26 No. 12, Dec. 1978 pp. 945-951.
W. B. Gaunt et al., The D3 Channel Bank, Bell Laboratories Record, vol. 50, No. 7, Aug. 1972 pp. 229-233.

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