Adaptive dead time control for switching circuits

Amplifiers – Modulator-demodulator-type amplifier

Reexamination Certificate

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Details

C330S20700P, C327S112000, C326S083000

Reexamination Certificate

active

06294954

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to apparatus and methods for adaptively reducing dead time in switching circuits.
2. Description of the Prior Art
FIG. 1
(prior art) shows a power output stage, typical for a switching audio amplifier. PWM Control Block
101
is the control circuitry that changes the input (in this case audio) into pulse width modulated control signals. The input may be analog or digital. Drivers
102
and
103
turn on and off the gates of switches
104
and
105
. In this case, the switches are FETs, but other active devices may be used. The use of FETs is typical for audio amplification. Filter
106
, normally an LC lowpass filter, removes the switching frequencies from the signal. Load
107
receives the power; in the audio case this is a speaker system. Snuber network
108
is optional, and is used to control the switching waveshape. Catch diodes
110
and
111
control the range of voltages during transitions, as filter
106
is usually inductive. These catch diodes are often integrated into transistors
104
and
105
.
It is important that output devices
104
and
105
not be on, or in conduction, at the same time, as high current will flow between the supplies and through the devices, causing a lack of efficiency, or even destruction of the devices. A dead time, meaning a time when neither device is on, is used to guarantee this does not occur.
FIG. 2
(prior art) illustrates this principal. Each switch
104
,
105
is turned off for a period
201
before the other is turned on. Period
201
is called the dead time.
It is important that dead time
201
be as small as possible, without overlap of on signals occurring. During the dead time, the voltage to the filter is not well controlled. This causes distortion in the output. In current designs, using very high drive current in drivers
102
and
103
, and making the switching times very short minimizes dead time. This approach has the undesirable effect of increasing the demands on the power supply and wiring, and also emits more RF radiation.
A need remains in the art for apparatus and methods for minimizing the dead time in switching circuits, without causing overlap of the on conduction in the switches.
SUMMARY OF THE INVENTION
Apparatus for adaptively reducing dead time in a switching circuit according to the present invention includes overlap detection circuitry for measuring the dead time/overlap, and control circuitry for setting the dead time to the optimum level (generally the minimum possible dead time without any overlap occurring).
The optimum dead time is set as follows. At the power on of the amplifier, the maximum possible dead time is set. The dead time is then incrementally reduced, and the dead time/overlap is measured at each incremental amount of dead time. When a very small predetermined amount of dead time is sensed, the dead time is set for the circuit.
A current meter may be placed in series with the switches. As the timing is changed from dead time to overlap, there will be a change in the current sensed. The point at the knee of the current versus dead time/ overlap curve will be near optimal in terms of distortion and efficiency. More overlap will give slightly better performance, and lower efficiency. The operating point can be chosen for the desired tradeoffs. The current sense may be done by sensing the voltage across a small resistor, or by using a current transformer.
As a variant of the current measuring scheme in a multichannel amplifier, a current sensor may be shared between all of the channels by placing it in the common power supply (e.g. to measure current into the power supply). One channel at a time is adjusted.
The voltage waveform at the switch point may also be monitored. The waveform can be digitized by an A/D converter, and the changes in the curve and overshoot monitored to select the desired control.
Another method for using a voltage measurement is as follows. An average value of the output voltage is generated by passing the output through an analog lowpass filter. A waveshape representing the average (filtered) voltage can then be used as a sensitive measure of switch timing.
The control circuitry for setting the dead time to the optimum level may be implemented as follows. A delay element is placed between the PWM circuitry and each driver. The rise and fall delay of each element may be controlled separately by control block. The circuitry may use either a digital delay or an analog delay.
In a second embodiment of the control circuitry, the drive current into each control gate of the switching device is controlled, by controlling the timing of the drivers. The gate of a power FET has very significant capacitance, often storing more than 100 nC of charge. The drive current necessary to charge and discharge this gate charge is significant, often in excess of 1 Amp. The timing of each control gate can be varied by varying the charge and discharge current for the gate. This may be accomplished by using multiple transistors in the drive circuitry, and using logic to control the number of drive transistors in use (turned on). As an example, if four matched devices are used, one device will take approximately four times as long to charge the gate as four devices would. This variable drive can also be used to control the output slew rate, giving further control.


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