Adaptive data slicer

Details Adaptive data slicer Adaptive data slicer

2000-04-17

2004-05-11

Chin, Stephen (Department: 2734)

Pulse or digital communications

Receivers

C360S039000

Reexamination Certificate

active

06735260

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to data communication systems and more particularly relates to an adaptive data slicer circuit based on peak detectors having dynamic selection of operating parameters.
BACKGROUND OF THE INVENTION
Data slicers, well known in the electrical arts, are commonly used in communications receivers to recover the digital data at the output of a demodulator. For example, in a frequency shift keying (FSK) receiver, such as that used in a communications system constructed in accordance with the Bluetooth specification, a common realization of the demodulator is as a frequency discriminator operating at some intermediate frequency (IF). The discriminator functions to recover the original baseband signal from the IF signal.
In the typical system, the signal at the output of the demodulator can be represented as a combination of (1) the original baseband signal used to convey the data transmitted by the transmitter; (2) additive noise and interference contributed by the wireless channel; and (3) the distortion caused by the actual circuitry the signal passes through. At the output of the demodulator, a decision circuit known as a ‘data slicer’ is typically used to convert the baseband signal into a stream of data bits. It is the goal of the data slicer to perform this conversion such that the content of the data bits match closely as possible the content of the original transmitted data.
In addition to reproducing the transmitted data with a minimum bit error rate (BER), the data slicer should be able to overcome variations in the properties or characteristics of the signal. Such variations may be due to receiving signals from multiple transmitters and may include variations in modulation factors and carrier frequency errors such as drift. Thus, it is desirable to have a data slicer whose slicing threshold (which is used to compare the baseband signal with) is determined adaptively and is not fixed at a predetermined level. The optimum slicing threshold level should be determined independently for each received packet and should be adapted throughout reception of the packet to compensate for possible frequency droop during its transmission.
As described above, the frequency offset and other parameters of the received signal in a communications system could have an effect on the DC level of the recovered baseband signal at the output of the demodulator (e.g., at the output of a FM discriminator). Consequently, the optimal slicing threshold is not fixed and typically varies over time. Depending on the application, it is preferable and sometimes necessary, for the slicing circuit to be sufficiently dynamic and adaptive to determine the optimum threshold for data slicing for each packet received, usually at the beginning of the packet during the preamble.
With the advent today, however, of wireless communications systems employing packets having a shortened length and shortened time slots, this becomes difficult to achieve with prior art slicing circuits. For example, the packets used in the Bluetooth protocol comprise a short 4-bit preamble and are transmitted using a spread spectrum frequency hopping scheme wherein the slot times are 625 &mgr;sec. The high hopping rate, short slot times and short preamble dictate that the data slicer be able to very quickly adapt the slicing decision threshold used to generate the received digital data.
On the other hand, in order to minimize the BER in the recovery of the payload contents of the packet, the slicing threshold should remain close to optimal with minimal variations thereto. This, however, creates conflicting requirements for the time constants associated with the determination of the slicing threshold. On the one hand, it is desirable to have quick adaptation of the slicing threshold during packet acquisition (i.e., during the preamble, etc.) and on the other hand it is desirable to have slow adaptation of the slicing threshold during reception of the payload in order to minimize the BER.
For example, in the Bluetooth protocol, the payload is preceded by an access code that is able to tolerate a higher BER. It is desirable, therefore, to determine the optimal slicing threshold level during reception of the access code even though the BER may be relatively high. After a valid access code is detected, it is desirable if the slicer could utilize longer time constants thus yielding a more stable slicing level during the reception of the payload portion of the packet.
Several examples of prior art adaptive slicing circuits will now be presented. A block diagram illustrating a first prior art data slicer circuit that utilizes a RC combination for smoothing the input voltage is shown in FIG.
1
. The data slicer, generally referenced
10
, comprises a slicing comparator
16
and a RC combination made up of resistor
12
having a value R and capacitor
14
having a value C. In operation, the RC functions to smooth the input voltage V
IN
such that an average of the voltage over time is input to the inverting terminal of the op amp. The principle is that over time, the capacitor functions to smooth the input voltage. Over time, the voltage across the capacitor represents the average of the input voltage and is used as the threshold or slicing voltage for determining the output data. The slicing comparator functions to compare the input voltage to the average voltage developed across the capacitor. If the input voltage is greater, a ‘1’ is output and if the input voltage is lower, a ‘0’ is output.
A disadvantage of this data slicer circuit is that is cannot quickly adapt to packets having a relatively short length. Optimum performance is achieved only when the circuit is configured to adapt slowly and using long packets having substantially equal numbers of 0's and 1's. The performance of the circuit severely degrades with short packets that may contain long sequences of 0's or 1's. In such a circuit, the use of a fast time constant for C results in degraded performance in terms of BER and may result in the loss of synchronization.
A block diagram illustrating a second prior art data slicer circuit that utilizes a DC blocking capacitor is shown in FIG.
2
. The data slicer, generally referenced comprises a slicing comparator
26
(hard limiter or 1 bit A/D), capacitor
22
having a value C and a resistor
24
having a value R. In operation, the capacitor cancels the DC level since the voltage across the capacitor is subtracted from the input voltage. The input voltage across the resistor now swings through zero. To generate the output data, the voltage across R is compared with the slicing voltage that can comprise a voltage fixed at ground level. Since the capacitor functions to cancel the DC, any fluctuations represent peaks of the signal. The slicing comparator outputs a ‘1’ for voltage swings above ground and a ‘0’ for swings lower than ground.
The disadvantages of this circuit are similar to those of the first prior art slicer described above. The circuit cannot quickly adapt to packets having a relatively short length. High performance is achieved only with slow adaptation, i.e., long time constant for C, and when using long packets having substantially equal numbers of 0's and 1's. The performance of the circuit severely degrades with short packets that may contain long sequences of 0's or 1's. In such a circuit, the use of a fast time constant for C results in degraded performance in terms of BER and may result in the loss of synchronization.
A block diagram illustrating a third prior art data slicer circuit that utilizes two diodes in parallel is shown in FIG.
3
. The data slicer, generally referenced
30
, comprises a slicing comparator
38
, diodes
32
,
34
and capacitor
36
having a value C. In operation, the capacitor is charged and discharged through the diodes so that its voltage tracks the average of the peaks of the input signal. For optimal operation of the circuit, the peak to peak voltage of the input signal is preferably two ti

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