Adaptive correlation of pattern resist structures using...

Details Adaptive correlation of pattern resist structures using... Adaptive correlation of pattern resist structures using...

2003-02-04

2004-09-14

Niebling, John F. (Department: 2812)

Optics: measuring and testing

Lens or reflective image former testing

Reexamination Certificate

active

06791679

ABSTRACT:

BACKGROUND
1. Field of the Invention
The invention relates to integrated circuit (IC) metrology and more particularly to a method and system for quality monitoring of photolithography processing.
2. Related Art
Growing demands for silicon wafers with large-scale integration necessitates submicron integrated circuit (IC) features with high precision and uniformity. As the features become smaller, it is increasingly critical to monitor the photolithographic process under which such semiconductor wafers are created.
In a typical photolithographic process, a series of masks are applied in a preset sequence to a silicon wafer, each mask is used to transfer its circuitry pattern onto a photosensitive layer (i.e., a photoresist layer) that is coated onto a layer (e.g., metal layer, etc.) formed on the silicon wafer.
FIG. 1
is a flow chart
100
illustrating conventional process steps for transferring a circuitry pattern from a mask to a silicon wafer. A silicon wafer is coated with photoresist in Step
110
, and the wafer is then exposed to light emitted from a device such as a scanner or stepper in Step
120
. The photoresist on the wafer is then developed to form structures on the photoresist layer in Step
130
, and the developed wafer is inspected to ensure the measurements of critical dimension (CD) of the structures are within that set by a design rule. The design rule regulates features such as the minimum width of a line or the minimum spacing between two lines in order to ensure that the lines do not overlap or unintentionally interact. The wafer is then selectively etched according to the pattern imprinted on the photoresist layer in Step
140
. Subsequent to etching, the silicon wafer is stripped of any remaining photoresist in Step
150
, and the CD measurements are again inspected in a final inspect Step
160
.
As feature sizes shrink, inspection and correction of surface features cross-sectional shape (“profile”), as well as CD measurements are crucial to higher yield and device performance.
Conventional methods employ a scanning electron microscope (SEM) known as a critical dimension scanning electron microscope (CD-SEM) to inspect and measure the profile and CD measurements on a wafer. However, CD-SEM is costly and must be employed in a vacuum environment.
SUMMARY
In one exemplary embodiment, one or more test wafers are measured during a develop inspect (DI) phase and a final inspect (FI) phase in order to establish a correlation between the DI measurements and the FI measurements. A process wafer can be measured during the DI phase, and a set of FI profile parameters are predicted according to the DI profile parameters and the established correlation between the DI phase and the FI phase. The DI profile parameters, along with the predicted FI measurements are used to improve the photolithographic process by adjusting fabrication parameters or “recipe” such as etch time, or by altering and repeating the steps of the photolithographic process. Moreover, the correlation between the DI phase measurements and FI phase measurements is adaptively revised when actual DI profile parameters and FI profile parameters of each wafer are accumulated.


REFERENCES:
patent: 6606152 (2003-08-01), Littau et al.
patent: 6606727 (2003-08-01), Yang et al.

Affiliated with

Also associated with

Rating

Adaptive correlation of pattern resist structures using... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Adaptive correlation of pattern resist structures using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Adaptive correlation of pattern resist structures using... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3259619