Adaptive configurable gate array

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular chip input/output means

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Details

257204, 257205, H01L 2710, H01L 2715

Patent

active

054593409

ABSTRACT:
A new configurable gate array is defined in a master slice wafer form without borders of the kind currently known between constituent transistor gates, effectively providing a sea of gates over the wafer, interrupted if at all by islands, containing markers or the like; and a resultant application specific integrated circuit formed of such master slice is defined. In the IC, transistor gate cells, which are the same type of cells used for other purposes in the IC, are configured to serve the input and output function. Accordingly, the input and output function may be placed on any location in the IC. As an incident to personalization of the wafer saw lanes are formed of channels that extend over transistor cells and the latter cells are consequently destroyed in slicing the wafer.

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