Electrical computers and digital processing systems: processing – Architecture based instruction processing – Data flow based system
Reexamination Certificate
2005-03-29
2005-03-29
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Architecture based instruction processing
Data flow based system
C712S011000, C712S015000, C712S018000, C712S035000, C712S221000
Reexamination Certificate
active
06874079
ABSTRACT:
Aspects of a method and system for digital signal processing within an adaptive computing engine are described. These aspects include a mini-matrix, the mini-matrix comprising a set of composite blocks, each composite block capable of executing a predetermined set of instructions. A sequencer is included for controlling the set of composite blocks and directing instructions among the set of composite blocks based on a data-flow graph. Further, a data network is included and transmits data to and from the set of composite blocks and to the sequencer, while a status network routes status word data resulting from instruction execution in the set of composite blocks. With the present invention, an effective combination of hardware resources is provided in a manner that provides multi-bit digital signal processing capabilities for an embedded system environment, particularly in an implementation of an adaptive computing engine. These and other advantages will become readily apparent from the following detailed description and accompanying drawings.
REFERENCES:
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patent: 6366999 (2002-04-01), Drabenstott et al.
patent: 6510510 (2003-01-01), Garde
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Kim Kenneth S.
Quicksilver Technology
Sawyer Law Group LLP
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