Adaptive clock skew and duty cycle compensation for a serial dat

Details Adaptive clock skew and duty cycle compensation for a serial dat Adaptive clock skew and duty cycle compensation for a serial dat

1993-03-09

1995-11-14

Kriess, Kevin A.

Boots, shoes, and leggings

364DIG1, 364271, 3642714, H03K 513

Patent

active

054674646

ABSTRACT:
The de-skewer utilizes a delay line to generate a set of delayed versions of an input clock signal. A bank of flip-flops compares pulses within the delayed clock signals to a synchronization pulse provided within an input data signal. A detector receives outputs from the flip-flops and selects the delayed clock signal having the least amount of skew based on the values of the output from the flip-flops. A multiplexer outputs the selected delayed clock. The de-skewer provides a simple, open-loop circuit for eliminating skew between parallel transmission paths. The de-skewer is ideally suited for eliminating skew from sources which do not vary significantly as a function of time. In particular, the de-skewer is well-suited for use in a data transmission system providing short bursts of high data rate transmissions. A double-edged de-skewer is also described which is capable of generating a pair of clock signals for use in eliminating duty cycle distortion.

REFERENCES:
patent: 5122679 (1992-06-01), Ishii et al.

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