Adaptive clock recovery for circuit emulation service

Details Adaptive clock recovery for circuit emulation service Adaptive clock recovery for circuit emulation service

1999-11-19

2004-04-13

Chin, Wellington (Department: 2664)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S518000, C370S503000, C370S474000

Reexamination Certificate

active

06721328

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to the field of telecommunications and in particular, to adaptive clock recovery for circuit emulation service.
BACKGROUND OF THE INVENTION
Asynchronous Transfer Mode (ATM) is a packet oriented technology for the realization of Broadband Integrated Services Network (“BISDN”). By using ATM, various services including voice, video, and data, can be multiplexed, switched, and transported together in a universal format thus permitting network resources to be shared among multiple users. The full integration of various services may also allow simpler and more efficient network and service administration and management. A constant bit rate (“CBR”) signal transported through a broadband ATM network is usually referred to as circuit emulation. Accommodation of CBR services is, however, an important feature of ATM, both for universal integration and for compatibility between existing and future networks. A CBR signal transported through a broadband network is first segmented into 47-octet units and then mapped, along with an octet of ATM Type
1
Adaption Layer (“AAL”) overhead, into the 48-octet payload of the cell. An ATM switcher multiplexes the cell through the ATM network. Typically, a source node sends data regulated by a service clock through an ATM network to a destination node.
A clock controlling a destination node buffer must operate at a frequency matched to that of the service signal input at the source node to avoid loss of information. ATM networks inherently transfer data across the network in a “bursty” fashion, i.e., not at a constant bit rate. Thus, when a CBR service is implemented in a packet network, such as an ATM network, a buffer is used at the destination node to store data temporarily. The data in the buffer is read out at a constant bit rate established by a local clock at the destination node. The bursty nature of the ATM network and other packet networks has introduced problems in using an adaptive clock recovery scheme to synchronize the local clock at the destination node with the service clock at the source node.
ATM networks introduce random delays in the transmission of data packets between two nodes. This is referred to as Cell Transfer Delay Variation (“CTDV”). Unfortunately, the CTDV may introduce significant wander components into a clock signal at a destination node that uses an adaptive clock recovery scheme. When significant wander components are contained in the CTDV, the clock signal generated by current adaptive clock recovery schemes at the destination node may follow CTDV, not the service clock of the source node. Service clock wander is masked by unrelated “errors” introduced by CTDV, and the resulting recovered clock at the destination node probably exceeds limits placed on the system wander levels, and may contain a jitter as well.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present invention, there is a need in the art for improvements in adaptive clock recovery for circuit emulation service (“CES”).
SUMMARY OF THE INVENTION
The above-mentioned problems associated with adaptive clock recovery for circuit emulation service are addressed by the present invention. A circuit and method for adaptive clock recovery for CES that uses a peak buffer fill level as an indicator to lock a local clock at a destination node with the service clock at a source node is disclosed.
In particular, an illustrative embodiment of the present invention includes a method for clock recovery in a packet network. The method includes a network which receives data packets at a destination node. The data packets are stored in a buffer. The data packets are read out of the buffer by using a locally generated clock. The fill level of the buffer is monitored over a first period of time. A relative maximum fill level for the buffer is identified during the first period of time. Further, the relative maximum fill level is used to control the frequency of the locally generated clock so as to control the rate at which data is read out of the buffer. This unique clock control algorithm and mechanism produces a recovered clock which contains no jitter.


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