Adaptive clock duty cycle controller

Details Adaptive clock duty cycle controller Adaptive clock duty cycle controller

1993-05-26

1994-05-24

Wambach, Margaret Rose

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307358, 328 11, H03K 3017, H03K 5153

Patent

active

053151640

ABSTRACT:
An adaptive clock duty cycle controller which generates a dc error signal that is supplied to a logic device, such as a logic inverter or a logic buffer, which outputs a specified duty cycle clock signal. The output of the logic device is supplied to a positive peak detector, a negative peak detector and an average signal level detector. The output of the positive peak detector and the negative peak detector are supplied to a mid-peak generating circuit which generates a signal for setting and maintaining the desired duty cycle. The signal output by the average signal level detector represents the average value of the output of the logic device. The signal output by the mid-peak generating circuit is compared with the signal output by the average signal level detector by an operational amplifier. The output of the operational amplifier represents the error signal which is supplied back to the input of the logic device to control the output of the logic device to the desired duty cycle.

REFERENCES:
patent: 4071781 (1978-01-01), Kayalioglu

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