Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Patent
1996-10-22
1999-07-13
Pham, Chi H.
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
370518, 375372, 375358, H04J 306, H04L 2536
Patent
active
059236698
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
There are two separate justification techniques at the Virtual Container 12 (VC12) level within Synchronous Digital Hierarchy (SDH). These are byte and bit justification and they are both used at the same time within SDH, but not in the initial justification process at the entry point to the SDH network.
By initially using both techniques, Complementary Justification eliminates the possibility of a large amount of wander being introduced by an SDH network.
Reducing the amount of network wander enables the size of any boundary buffer to be reduced.
The fitting of boundary buffers on the exit from an SDH or other network can greatly reduce the relative wander by of the order of 80% for SDH or other networks on the links not currently being used for synchronisation, whilst not reducing relative wander on the links used for synchronisation.
Complementary Justification is described in our co-filed application, U.S. Ser. No. 08/762,967, filed Dec. 6, 1996, now allowed which is a continuation-in-part of U.S. Ser. No. 08/408,732, filed Mar. 22, 1995, abandoned, which corresponds to GB Publication No. 228,786, imported herein by reference.
Wander on the output of a transmission link may or may not cause slips. The most important factor is how the wander moves relative to the clocking source of the receiving equipment.
If the clock source of the receiving unit is made available to a boundary buffering device, then it is possible that the buffer can phase adjust the output of the transmission link so that it tracks fairly closely to tie receiving equipment clocking source and when this is possible slips can virtually be eliminated. This reduces the relative wander between the tributary and the clock of the receiving equipment.
Examples of five Receiving Equipment configurations are recovered clock to drive the return interface. drive the return interface. read clock is from another input or internal source. This clock is also used to drive the return interface. the aligner read clock for another input and is also used to drive the return interface. read clock is from another input or internal source. The received input clock is used to drive the return interface.
The effects of these configurations on the ideal clock characteristics of the Boundary Buffer Unit are: the network. the benefit of a Boundary Buffer.)
These Characteristics lead to the three ideal requirements. The Boundary Buffer link being used as a reference. (The buffer should introduce a constant delay.) 2048 kbit/s link being used as a synchronisation reference in order to match the return clock.
In order to make configuration simple and to allow for the receiving equipment to dynamically change its reference selection, the boundary buffer must automatically change between `b` and `c` as required. This means that the Boundary Buffer algorithm must compensate for whether the tributary is being used to carry a reference or not. The Boundary Buffer must determine from the return clock whether its tributary is being used as the reference.
An ordinary boundary buffer will meet only requirements `a` and `c`, as it is not intended to work on reference links. Its usage can lead to provisioning problems. An ordinary boundary buffer is a simplified form of what is described below.
SUMMARY OF THE INVENTION
According to the present invention there is provided a boundary buffer control unit for use in a telecommunications system employing Synchronous Digital Hierarchy (SDH), or other multiplexing means, comprising a phase adjusting means having means for determining the phase error between a recovered line clock and a recovered return clock from receiving equipment of the telecommunications system, the phase of the recovered return clock being advanced or retarded by the value of the phase error and the phase of the recovered line clock being retarded or advanced respectively by less than the value of the phase error, so as to produce a phase adjusted Line Clock.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will now be
REFERENCES:
patent: 4831637 (1989-05-01), Lawrence et al.
patent: 5245636 (1993-09-01), Sari et al.
patent: 5268936 (1993-12-01), Bernardy
patent: 5517521 (1996-05-01), Strawn
Annual Review of Communications, vol. 47, 1993--1994, Illinois, U.S., pp. 783-789, XP 000455396, Beecher, P.A., "Sonet Conformance Testing", see p. 786, right col., par. 4--p. 787, left col., par. 1, Fig. 3.
ICC'79. 1979 International Conference on Communications, Boston, MA, USA, 10-14, Jun. 1979, vol. 1, 1979, New York, NY, IEEE, pp. 11.6/1-6, Okimi K, et al., "Toward future standardization of synchronous digital terminals", see p. 11.6.2, right col., par. 3.1--p. 11.6.3, left col., par. 3.2, see p. 116.5, right col., par. 4.4; Figs. 4, 5, 10A, 10B.
GPT Limited
Nguyen Steven
Pham Chi H.
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