Adaptive bit synchronizer

Details Adaptive bit synchronizer Adaptive bit synchronizer

1985-07-31

1987-06-09

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

375 83, 375 87, 375119, H04L 2722, H03D 322

Patent

active

046726373

ABSTRACT:
An adaptive bit synchronizer is operable to extract digital data and its associated clock from a transmitted digital signal, and includes a tunable matched filter set for modifying the input signal to correct for deviations in offset and gain, which filter set includes data, transition and derivative matched filters. A sampling device samples the output of the data matched filter for making bit decision and for estimating the reliability thereof. A clock-producing device is connected with the matched filter set for producing at least two clocks, use being made of an optimum phase detector for estimating the time error between the proper clock edge and the actual clock edges. A loop filter circuit smooths the estimates of the proper clock time to generate clock signals, and a device responsive to the average square error of the clock signals varies the loop parameters of the loop filter means to minimize average square phase error.

REFERENCES:
patent: 3878334 (1975-04-01), Halpern
patent: 4320345 (1982-03-01), Waggener
patent: 4584534 (1986-04-01), Lijphart et al.

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