Adaptive bias current generator methods and apparatus

Electricity: power supply or regulation systems – External or operator controlled

Reexamination Certificate

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Reexamination Certificate

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08044654

ABSTRACT:
In one aspect, a method of reducing power consumption in a circuit by adaptive bias current generation of a bias current configured to bias, at least in part, at least one amplifier of the circuit is provided. The method comprises establishing the bias current based, at least in part, on a reference frequency of a reference clock providing a clock signal to at least one component of the circuit, and changing the bias current in response to a change in the reference frequency of the at least one reference clock, the bias current being change non-linearly with respect to the change in the reference frequency of the at least one reference clock. In another aspect, the method comprises establishing the bias current based, at least in part, on a capacitance of a reference capacitor, and changing the bias current in response to a change in the capacitance of the reference capacitor such that the bias current is changed non-linearly with respect to changes in the capacitance of the reference capacitor.

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Anderson et al.., A Cost-Effective High-Speed 12-bit Pipeline ADC in 0.18-um Digital CMOS, IEEE Journal of Solid-State Circuits, Jul. 2005, pp. 1506-1513, vol. 40, No. 7.

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