Adaptive bandwidth phase locked loop with feedforward divider

Details Adaptive bandwidth phase locked loop with feedforward divider Adaptive bandwidth phase locked loop with feedforward divider

2006-12-11

2009-10-13

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural oscillators controlled

C331S016000, C331S034000, C331S17700V, C331S046000, C327S156000, C375S376000

Reexamination Certificate

active

07602253

ABSTRACT:
In some embodiments, a chip includes first and second sub phase lock loops (sub-PLLs) including first and second voltage controlled oscillators (VCOs) to provide first and second VCO output signals and first and second feedforward divider circuits to divide first and second frequencies of the first and second VCO output signals by first and second division factors. The chip also includes phase locked loop control circuitry to select the first and second division factors. Other embodiments are described and claimed.

REFERENCES:
patent: 5610558 (1997-03-01), Mittel et al.
patent: 6281727 (2001-08-01), Hattori
patent: 6670833 (2003-12-01), Kurd et al.
patent: 6762634 (2004-07-01), Hattori
patent: 6812797 (2004-11-01), De Veirman et al.
patent: 7006590 (2006-02-01), Skierszkan et al.
patent: 2001/0008384 (2001-07-01), Ku
patent: 2005/0135526 (2005-06-01), Miller et al.
patent: 2005/0182983 (2005-08-01), Gaskins et al.
patent: 1544717 (2005-06-01), None
patent: 2295930 (1996-06-01), None
patent: 60197015 (1985-10-01), None
S. Sidiropoulos, et al., Adaptive Bandwidth DLLs and PLLs Using Regulated Supply CMOS Buffers, 2000 Symp. On VLSI Circuits Digest of Papers, Jun. 2000, pp. 124-127.
J.G. Maneatis, et al., Self-biased, High-Bandwidth, Low-Jitter 1-to-4096 Multiplier Clock-Generator PLL, IEEE J. of Solid-State Circuits Digest of Papers, vol. 38, No. 11, Nov. 2003, pp. 1795-1803.
T. H. Lin et al., A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop, IEEE J. of Solid-State Circuits, vol. 36, No. 3, Mar. 2001, pp. 424-431.
E. Alon, et al., Replica Compensated Linear Regulators for Supply-Regulated Phase-Locked Loops, IEEE J. of Solid-State Circuits, vol. 41, No. 2, Feb. 2006, pp. 413-424.
J. Kim, et al., A 20-GHz Phase-Locked Loop for 40Gb/s Serializing Transmitter in 0.13μm CMOS, 2005 Symp. On VLSI Circuits Digest of Papers, Jun. 2005, pp. 144-147.
J. Kim, Powerpoint presentation given to Samsung Electronics, Inc., May 2005, “Design of CMOS Adaptive Bandwidth PLLs/DLLs.” 51 pages.
“8029P010EP EP Search Report Mailed Feb. 18, 2008 for EP Application 07254315.0-2206”, (Feb. 18, 2008), Whole Document.
“8029P010EP OA mailed Dec. 15, 2008 for EP Application 07254315.0-2206”, (Dec. 15, 2008), Whole Document.
Kim, Jaeha , et al., “Circuit Techniques for a 40Gb/s Transmitter in 0.13μm CMOS”,ISSCC 2005/Session 8/Circuits for High-Speed Links and Clock-Generators/8.1, 2005 IEEE International Solid-State Circuits Conference, (2005), 150, 151 and 589.

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