Adaptive analog minimum/maximum selector and subtractor circuit

Details Adaptive analog minimum/maximum selector and subtractor circuit Adaptive analog minimum/maximum selector and subtractor circuit

1993-06-25

1995-04-18

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327355, H03K 524

Patent

active

054081947

ABSTRACT:
A circuit for use as a channel of a minimum selector and subtractor circuit includes a P-Channel MOS transistor having a gate connected to an input node, a source connected to the output of a current source, and a drain connected to a fixed voltage source. The source of the P-Channel transistor is connectable to a common conductive line through a first switch. The source of the P-Channel transistor is also connected to the non-inverting input of a transconductance amplifier. The inverting input of the transconductance amplifier is connected to a first plate of a capacitor. The second plate of the capacitor is connected to a fixed voltage source such as ground. The output of the transconductance amplifier is connectable to its inverting input through a second switch. The output of the transconductance amplifier forms the output of the minimum selector and subtractor circuit. A plurality of individual channel circuits may all be connected to the common conductive line. The input nodes of the individual channel circuits are each individually connected to a different one of a plurality of analog input lines. The minimum selector and subtractor circuit determines the minimum analog value appearing on the plurality of lines and subtracts that value from the input values on all of the input lines. A maximum selector and subtractor circuit is formed by reversing transistor types.

REFERENCES:
patent: 4142116 (1979-02-01), Hardy, Jr. et al.
patent: 4691125 (1987-09-01), Rybicki
patent: 4857768 (1989-08-01), Griffith et al.
patent: 4890014 (1989-12-01), Ramet
patent: 4943736 (1990-07-01), Kihara et al.
patent: 5175451 (1992-12-01), Ihara

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