Adaptive addressable circuit redundancy method and apparatus wit

Details Adaptive addressable circuit redundancy method and apparatus wit Adaptive addressable circuit redundancy method and apparatus wit

1998-02-26

1999-10-19

Nelms, David

Static information storage and retrieval

Addressing

365200, G11C 800

Patent

active

059700130

ABSTRACT:
An adaptive addressable circuit redundancy method and apparatus, e.g., an adaptive memory redundancy method and apparatus, utilizes an on-chip processor to test, analyze and reassign spare addressable circuits to replace defective or intermittent addressable circuits. The present invention is applicable both in a manufacturing environment and/or in a field environment wherein the integrated circuit is operational. An adaptive addressable circuit redundancy module intercepts a data path between the on-chip processor and the addressable circuits to reassign defective addresses as necessary to utilize a spare addressable circuit bank. In another embodiment of the present invention, a broadcast write module cuts memory test time almost in half by writing a same data pattern to a significant portion or all of the addressable circuits, e.g., memory, substantially simultaneously.

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