Adaptable MMIC array

Details Adaptable MMIC array Adaptable MMIC array

1998-01-27

2001-01-30

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

C438S129000, C438S598000

Reexamination Certificate

active

06180437

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to microwave monolithic integrated circuits and more particularly to an improved footprint for a multipurpose partially fabricated chip.
BACKGROUND OF THE INVENTION
In the fabrication of microwave monolithic integrated circuits (MMICs), it is often necessary to design application-specific circuits of which only a relatively small number will ever be made. Integrated circuit design and manufacture is notoriously expensive, not only because it involves a great deal of work on the part of the engineering professionals and highly skilled technicians, but also because each manufactured circuit must be individually characterized to deal with inherent slight differences in the manufacturing process of the semiconductor layers.
To overcome this problem and make MMIC design more affordable, it has previously been proposed by Turner et al. in the article “Application Specific MMIC: A Unique and Affordable Approach to MMIC Development (IEEE Microwave and Millimeter-Wave Monolithic Circuits Symposium, 1988) to manufacture a footprint consisting of all of the chip circuitry, except for the metallic interconnection layer, in quantity on large wafers, and to build different kinds of circuits by subsequently covering the footprint with an appropriate metallic interconnection layer.
Basically, the footprint or MMIC array is a monolithic microwave integrated circuit (MMIC) chip which has a set pattern or array of unconnected field effect transistors (FETs), diodes and N+ and nichrome resistors. An entire wafer can have this array repeated across its surface. Multiple wafers can thus be processed and put into storage. When circuits are needed quickly for a program, a variety of masks for the formation of metallic and dielectric layers defining capacitors, interconnection between the footprint elements, and airbridges can be rapidly produced or taken from a library of pre-designed mask sets. Thus, a variety of metallic and dielectric patterns can be easily added to identical footprint chips to form a variety of microwave circuits, and the types of circuits and quantity of circuits needed can be quickly acquired. Another significant advantage to having an array which allows for many types of circuits to be realized and wafers to be fabricated and stored, is that once the first wafers finished with top metallization are characterized, then all the remaining wafers will have very similar electrical characteristics. This then removes much of the design risk inherent in MMIC design, i.e. the process variation from the nominal models used in design. Once the wafers are characterized, exact models can be used instead of statistical models.
In practice, an important aspect of the manufacture of footprint chips that lend themselves to the realization of a commercially viable number of different microwave circuits is the nature and placement of the chip components. Prior art approaches to the footprint technique encountered problems because the positioning of the circuit elements on the footprint made it difficult to design interconnection layers for many different applications. Also, it was difficult to change the value of the nichrome resistors on the chip from one application to another, or to so interconnect the chip components as to allow operation in the multi-gigahertz range.
Although prior art footprints have proven generally suitable for their intended purposes, they possess inherent deficiencies which detract from their overall effectiveness and desirability. Specifically, the prior art approach has several notable deficiencies which limit its practical applicability. For one, it includes low frequency components intermixed with microwave components of the footprint thereby wasting 25% to 75% of the available chip area. Each quadrant of the prior art footprint is specialized for a specific type of function, thereby reducing its flexibility and reusability.
Secondly, the prior art does not have dual axis symmetry (i.e. symmetry about both the x axis and the y axis). The prior art footprints have only x-axis symmetry. The lack of this symmetry degrades MMIC performance when the circuit design is balance driven (i.e. push-pull amplifiers, double balanced mixers, etc.). Mixers especially require dual axis symmetry due to their having 3 ports, each of which should be symmetrical. Another very important benefit of dual axis symmetry is the ability to mirror or rotate designs 180° to facilitate layout of larger scale integrations and allow manipulation of relative I/O port locations.
Thirdly, the prior art has gate connections on only one side of the FETs. This tends to introduce layout parasitics and leads to awkward circuit implementations.
Fourthly, the prior art footprints use a coplanar ground approach to allow the use of wafer probe testing; however, coplanar circuits require large amounts of “real estate” to form top-side ground planes.
Lastly, the above-mentioned prior art disclosure requires a total of seven separate footprints to realize a limited array of functions. The need for many different footprints reduces the usefulness of the adaptability concept. If a semiconductor wafer is populated with many different footprints and each one is only suited to a narrow range of applications, then the option to replicate only one or two designs across the entire wafer is not possible without wasting the remaining footprint sites. This would be important if a single design were needed in high volume.
It is therefore desirable to provide a footprint which is highly adaptable to a large variety of circuits with relatively simple interconnection designs.
SUMMARY OF THE INVENTION
In accordance with the invention, an optimum quantity, type and location of FETs, diodes, resistors, and substrate via holes has been developed to provide a footprint which allows almost any MMIC circuit to be realized by connecting components of the footprint with metallic or metallic and dielectric personalizing layers formed over the basic footprint. Knowing the position and values of the components, and the electrical parameters of a circuit to be created, conventional computer-aided design techniques can advantageously be used to produce a mask which will most efficiently provide the necessary interconnections.
More particularly, the present invention overcomes the above-identified deficiencies of the prior art by providing a footprint which has the following features:
1) A pair of substrate ground via holes are located near the gate connections to facilitate high frequency performance;
2) The FETs are made from many individual FET fingers or segments allowing FETs of different sizes to be fabricated by connecting two or more of them in parallel;
3) The FETs' gate connection is formed to allow the connection to be made from either side of the FET. This adds flexibility to the layout and allows for symmetry;
4) The footprint array is symmetrical about both the X and Y axes, thus allowing balanced and/or mirrored circuit layouts to be produced;
5) Nichrome (NiCr) resistors are located near the substrate via holes for DC bias as well as for microwave impedance matching;
6) The NiCr resistors are split into many small resistors to allow for proper thermal dissipation, thus assuring high reliability;
7) The value of the NiCr resistors in the footprint is made variable by changing the overlap of the top metallization;
8) The FETs' gate width is preferably 75 &mgr;m to allow for operation at frequencies up to about 20 GHz. Alternatively, a gate width of 50 &mgr;m can be used for frequencies in excess of 40 GHz;
9) The size of the components and the spacings between components allows for the formation of airbridges to span over unused components, as well as for metal lines to pass between components without interfering with the components;
10) The FET gates are spaced by a minimum of 17 &mgr;m to allow for good thermal dissipation, again assuring high reliability and also radio frequency (RF) isolation from neighboring FET sections.
In accordance with another aspect of th

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