Adaptable exerciser for a memory system

Registers – Systems controlled by data bearing records – Time analysis

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Details

3401461AX, 340174ED, G11C 2900, G06F 1110

Patent

active

040537510

ABSTRACT:
An adaptable exerciser for a memory system utilizes the error rates of independent memory segments to selectively exercise the segments at different frequencies. Each memory segment has an associated counter which is incremented with errors and decremented at a predetermined rate with time. If the count accumulated in a counter reaches a specified level, the associated memory segment will be exercised at a higher frequency. If the count in any counter should reach a second higher specified level, the associated memory segment is removed from service.

REFERENCES:
patent: 3248697 (1966-04-01), Montgomery
patent: 3372376 (1968-03-01), Helm
patent: 3534403 (1970-10-01), Matarese
patent: 3570008 (1971-03-01), Downing et al.
patent: 3792450 (1974-02-01), Bogar et al.
patent: 3906200 (1975-09-01), Petschauer
patent: 3909810 (1975-09-01), Naden et al.
patent: 3934224 (1976-01-01), Dulaney et al.

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