Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2000-01-03
2002-08-13
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S155000, C341S156000
Reexamination Certificate
active
06433727
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an AD converter and its control method and, and more particularly to an AD converter with a power saving circuit and its control method.
2. Description of the Related Art
FIG. 5
shows an example of the configuration of a conventional AD converter with sampling capacitors.
An AD converter
501
comprises an analog input side capacitor array
502
, a reference side capacitor array
503
, a comparator
504
, and a successive approximation control circuit
505
. The analog input side capacitor array
502
is an array composed of 4-bit-weighted capacitors
508
,
509
,
510
,
511
, and
512
. That is, the capacitors
508
and
509
are capacitors with the reference capacity value of C, the capacity
510
is a capacitor with the capacity value of 2C, the capacity
511
is a capacitor with the capacity value of 4C, and the capacity
512
is a capacitor with the capacity value of 8C. The one end of each of the above capacitors is connected to a selector
518
,
519
,
520
,
521
, or
522
, respectively and, in response to a control signal
534
from the successive approximation control circuit
505
, is connected to an analog input terminal
536
, a reference power source terminal
537
, or a ground terminal
538
.
The reference side capacitor array
503
is also an array composed of 4-bit-weighted capacitors
513
,
514
,
515
,
516
, and
517
. That is, the capacitors
513
and
514
are capacitors with the reference capacity value of C, the capacity
515
is a capacitor with the capacity value of 2C, the capacity
516
is a capacitor with the capacity value of 4C, and the capacity
517
is a capacitor with the capacity value of 8C. The one end of each of the above capacitors is connected to a selector
523
,
524
,
525
,
526
, or
527
, respectively and, in response to the control signal
534
from the successive approximation control circuit
505
, is connected to a ground terminal
539
.
The comparator
504
comprises an output-stage amplifier
543
and a pre-amplifier
542
that reduces the offset of the output-stage amplifier
543
. The output-stage amplifier
543
and the pre-amplifier
542
are connected via offset-canceling capacitors
545
and
546
. Analog switch
547
and
548
, provided for determining the operation point of the output-stage amplifier
543
and for canceling the offset of the pre-amplifier
542
, are turned on during offset canceling.
Switches
530
and
531
are switches used to fix the potential of a common electrodes
532
of the analog input side capacitor array
502
and a common electrode
533
of the reference side capacitor array
503
, respectively, to the intermediate potential
541
output from a bias circuit
540
when sampling the analog input voltage.
Next, the AD conversion operation of the conventional AD converter shown in
FIG. 5
will be described.
First, in the sampling mode, switches
530
and
531
are turned on. Then, the common electrode
532
of the analog input side capacitor array
502
and the common electrode
533
of the reference side capacitor array
503
are connected to the intermediate potential
541
output from the bias circuit
540
. The capacitors
508
-
512
are connected to the analog input voltage VAIN by the selectors
518
-
522
. The capacitors
513
-
517
are connected to the ground potential GND by the selectors
523
-
527
. Turning the switches
547
and
548
on sets inputs
549
and
550
of the output-stage amplifier
543
to the intermediate potential
541
output from the bias circuit
540
and, at the same time, stores the output offset of the pre-amplifier
542
in the offset-canceling capacitors
545
and
546
. At this time, let VS be the intermediate potential
541
output from the bias circuit
540
. Then, the total charge Q
13
accumulated in the analog input side capacitor array
502
is calculated as:
Q
13
=16
C×
(
VAIN−VS
) (25)
The total charge Q
14
accumulated in the reference side capacitor array
503
is calculated as:
Q
14
=16
C×
(−
VS
) (26)
Next, when the mode is changed to the comparison mode, switches
530
and
531
are turned off. Then, the capacitors
508
-
511
are connected to the ground potential GND by selectors
518
-
521
. The capacitor
512
is connected to the reference potential VR by the selector
522
. The capacitors
513
-
517
are connected to the ground potential GND by the selectors
523
-
527
. At this time, let VCM
1
be the potential of the common electrode
532
. Then, the total charge Q
15
accumulated in the analog input side capacitor array
502
is calculated as:
Q
15
=8
C×
(
VR−VCM
1
)−8
C×VCM
1
(27)
Let VCM
2
be the potential of the common electrode
533
. Then, the total charge Q
16
accumulated in the reference side capacitor array
503
is calculated as:
Q
16
=16
C×
(−
VCM
2
) (28)
Here,
Q
13
=
Q
15
(29)
Q
14
=
Q
16
(30)
by the law of charge conservation. The following is obtained by substituting equations (25)-(28) into equations (29) and (30):
VCM
1
=½
×VR−VAIN+VS
(31)
VCM
2
=
VS
(32)
The comparator
504
outputs the comparison result of “1” or “0” by comparing the potential VCM
1
of the common electrode
532
represented by equation (31) with the potential VCM
2
of the common electrode
533
represented by equation (32). As equations (31) and (32) show, when the analog input voltage VAIN equals the output voltage of the analog input side capacitor array (here, ½×VR), both the potentials VCM
1
and VCM
2
of the comparator side electrodes become VS as if the offset of the pre-amplifier
542
was canceled. The output offset of the pre-amplifier
542
, generated when the potential of the common electrodes
532
and
533
which are the inputs to the pre-amplifier
542
is VS, is accumulated in the offset-canceling capacitors
545
and
546
. Therefore, the potential of the inputs
549
and
550
of the output-stage amplifier
543
also become VS, and therefore the output offset of the pre-amplifier
542
may be ignored. The input offset of the output-stage amplifier
543
is reduced to a value generated by dividing it by the amplification ratio of the pre-amplifier
542
.
The successive approximation control circuit
505
determines the value of the most significant bit of the conversion result based on the output from the comparator
504
, and supplies the control signal
534
to the selectors
518
-
522
to perform the comparison operation corresponding to the bit in the next place.
If the analog input voltage VAIN is higher than ½×VR, the comparator
504
outputs “1” to output the control signal
534
to connect the capacitor
511
, corresponding to the bit in the next place, to the reference voltage VR while the capacitor
512
, corresponding to the most-significant bit, is still connected to the reference voltage VR. That is, in the second comparison, the analog input voltage VAIN is compared with ¾×VR. Conversely, if the analog input voltage VAIN is lower than ½×VR, the comparator
504
outputs “0” to output the control signal
534
to connect the capacitor
512
, corresponding to the most significant bit, to the ground potential GND and to connect the capacitor
511
, corresponding to the bit in the next place, to the reference voltage VR. In the second comparison, the analog input voltage VAIN is compared with ¼×VR. In this way, by repeating the operation in which the successive approximation control circuit
505
outputs the successive approximation control signal
534
and then determines the bit value based on the output of the comparator
504
for a specified number of times (four times in this example), the analog input voltage VAIN is converted to digital output signals
535
.
However, this prior art has the following problems:
The first problem
Nguyen John
Whitham, Curtis & Christofferson
Young Brian
LandOfFree
AD converter with a power saving circuit and its control method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with AD converter with a power saving circuit and its control method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and AD converter with a power saving circuit and its control method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2893643