Activity verification system for memory or logic

Details Activity verification system for memory or logic Activity verification system for memory or logic

1988-09-12

1990-08-07

Fleming, Michael R.

Excavating

371 165, G06F 1100

Patent

active

049473930

ABSTRACT:
The logic cards for a main storage unit or computer logic which receive request operations for access to portions of the memory or logic are divided into banks or elements. When a request operation attempts to access one of the elements a return busy signal is raised from that element. The present invention structure generates a predicted busy signal which occurs during the same time the return busy signal should be activated or operable. The return busy signal and predict busy signal are compared in novel circuitry to verify that the element performing the operaton is in fact performing an operation during the predetermined time slot allowed for performance of the requested operation. Fault signals for bank invalidation are stored in internal check trap circuitry for future reference when the requestor raises a subsequent request operation.

REFERENCES:
patent: 3536259 (1970-10-01), Okumura
patent: 3749897 (1973-07-01), Hirvela
patent: 4213178 (1980-07-01), Diez et al.
patent: 4538273 (1985-08-01), Lasser
patent: 4586180 (1986-04-01), Anders
patent: 4627060 (1986-12-01), Huang
patent: 4683568 (1987-07-01), Urban

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