Boots – shoes – and leggings
Patent
1995-03-10
1996-09-10
An, Meng-Ai T.
Boots, shoes, and leggings
3642319, 364DIG1, G06F 1580
Patent
active
055554288
ABSTRACT:
Disclosed is a masking technique for a SIMD processor (10) which is capable of masking a plurality of individual machine operations within a single instruction incorporating a plurality of operations. To accomplish this each different machine operation within the instruction includes a number of masking bits which address a specific location in a mask register (60). The mask register (60) includes a mask bit bank (62). The mask location selected within the mask register (60) is bit-wise ANDed with a mask context bit (66) in order to establish whether the processing element will be enabled or disabled for a particular conditional sub-routine which is called. One of the bit locations in the mask bit bank (60) is a hard-wired unconditional bit which overrides the mask context bit (66) in order to enable the processing elements in special situations. In addition, a scalar mask bit is provided to facilitate scalar processing. By this operation, instructional parallelism can be incorporated in order to increase through-put of the processor.
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Radigan James J.
Schwartz David A.
An Meng-Ai T.
Denson-Low W. K.
Duraiswamy V. D.
Harrity John
Hughes Aircraft Company
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