Activity masking with mask context of SIMD processors

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3642319, 364DIG1, G06F 1580

Patent

active

055554288

ABSTRACT:
Disclosed is a masking technique for a SIMD processor (10) which is capable of masking a plurality of individual machine operations within a single instruction incorporating a plurality of operations. To accomplish this each different machine operation within the instruction includes a number of masking bits which address a specific location in a mask register (60). The mask register (60) includes a mask bit bank (62). The mask location selected within the mask register (60) is bit-wise ANDed with a mask context bit (66) in order to establish whether the processing element will be enabled or disabled for a particular conditional sub-routine which is called. One of the bit locations in the mask bit bank (60) is a hard-wired unconditional bit which overrides the mask context bit (66) in order to enable the processing elements in special situations. In addition, a scalar mask bit is provided to facilitate scalar processing. By this operation, instructional parallelism can be incorporated in order to increase through-put of the processor.

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Nation et al., "Efficient Masking Techniques for Large-Scale SIMD Architectures", Third Symposium on the Frontiers of Massively Parallel Computations, IEEE Computer Society Press, Oct. 1990, pp. 259-264.
Horde, R. Michael, "Parallel Supercomputing in SIMD Architectures," 1990, CRC Press Inc., Boca Raton, FL., pp. 85-105 and 143-148.
Steven et al., "HARP: A Parallel Pipeline RISC Processor," Microprocessors and Microsystems, vol. 13, No. 9, Nov. 1989, pp. 579-587.
Przytula, K. Wojtek, "Medium Grain Parallel Architecture For Image and Signal Processing," Parallel Architectures and Algorithms For Image Understanding, 1991.

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