Actively driven VREF for input buffer noise immunity

Details Actively driven VREF for input buffer noise immunity Actively driven VREF for input buffer noise immunity

2001-01-12

2003-07-22

Nelms, David (Department: 2818)

Static information storage and retrieval

Powering

C365S185210, C365S189070, C365S206000, C365S207000

Reexamination Certificate

active

06597619

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to a method and apparatus for improving reference voltage stability in semiconductor devices. More specifically, the invention involves the integration of a circuit using a voltage reference to generate a constant voltage with a semiconductor device to actively drive a reference voltage in the device.
2. State of the Art
Semiconductor devices such as logic chips, processors, and memory devices commonly employ at least one voltage reference signal (“V
REF
”) for testing and operation. Use of a V
REF
signal in semiconductor devices is well known in the art. Problems associated with V
REF
stability caused by variances in a V
REF
source or noise on the semiconductor device are also well known. For example, a reference voltage generating circuit incorporated into a memory device (e.g. DRAM, SDRAM, or flash memory) generates V
REF
from a power supply voltage supplied to the memory device. Variations in the power supply voltage are translated to variations in V
REF.
These variations may cause the memory device to operate defectively. Likewise, noise from other signals on the memory device may also cause variations in the generated V
REF
resulting in similar operational defects.
In other memory devices, such as Rambus and double data rate (DDR) memory, a V
REF
signal is bused to the device rather than being generated on the device. The bused V
REF
is subject to the same noise and signal variations as a V
REF
generated on the device. This results in an equal propensity for operational defects due to V
REF
fluctuations.
The use of a V
REF
signal with a semiconductor device is best explained with reference to an example.
FIG. 5
is a simplified block diagram illustrating the workings of a memory device
500
such as an SDRAM as known in the art. The memory device
500
includes an address register
510
, row address controls
520
, column address controls
530
, at least one memory array
540
, data input/output controls
550
, control logic
560
and a V
REF
generator
570
. An external power supply provides a power supply voltage V
DD
to the memory device
500
. To reduce the number of terminals on the memory device, a reference voltage (V
REF
) is created from the power supply voltage V
DD
rather than from a power supply independent of that producing V
DD
. V
DD
is introduced to the V
REF
generator
570
which generates a V
REF
, signal having a desired voltage. For example, the V
REF
generator
570
may be a voltage divider which produces V
REF
having half of the voltage of V
DD
. The generated V
REF
signal is routed to both the address register
510
and the data input/output controls
550
where it is used in the operation of the memory device
500
.
A simplistic generalization of V
REF
operation in a memory device demonstrates some of the problems associated with varying V
REF
signals. The V
REF
signal generated from V
DD
by the V
REF
generator
570
has a voltage which is approximately half of the power supply voltage V
DD
applied to the memory device
500
. A signal, such as an address signal corresponding to a memory cell location in the memory array
540
, received by the memory device
500
at the address register
510
, is compared to V
REF
. If the signal has a voltage which is higher than V
REF
, then the signal is high and corresponds to a logical value of one. If the signal has a voltage lower than V
REF
, then the signal is low, having a logical value of zero. In this manner, received signals may be compared to V
REF
and assigned values which define memory locations within the memory array
540
. Similarly, data read from or written to the memory device
500
is compared to V
REF
to establish whether each data bit is high or low.
Because V
REF
is usually generated from the power supply voltage V
DD
, variances in the power supply voltage V
DD
cause fluctuations in V
REF
. If the variance is great enough to drive V
REF
closer to the power supply voltage V
DD
, a signal received by the memory device
500
which normally would have been defined as high may, instead, be mischaracterized as low. The altered characterization of the signal results in a malfunction of the memory device
500
. Similarly, noise created by other circuits and power supplies on the memory device may also cause variances in V
DD
which in turn cause variances in V
REF
resulting in the mischaracterization of signals received by the memory device.
To reduce the problems associated with V
REF
variations in semiconductor devices, integrated circuits and memory devices, numerous V
REF
regulation circuits have been devised to aid in stabilizing V
REF
. These circuits may be separate from, or coincidental with, the V
REF
generation circuits for the integrated circuits. One example of a circuit designed to compensate for variation in V
REF
involves the addition of decoupling capacitors between the power rails of an integrated circuit. The capacitors help eliminate stray capacitance, thereby reducing the amount of noise within the memory device. Similarly, resistive decoupling of noisy nodes within a memory device eliminates noise at the noisy node but enhances noise elsewhere in the circuit. Likewise, diodes are used to reduce the amount of noise in such circuits. Other examples of stabilized V
REF
generation circuits are described in U.S. Pat. Nos. 5,212,440 and 4,477,736, the disclosures of each of which are hereby incorporated herein by reference. However, these circuits do not eliminate all of the noise in V
REF
.
Although a number of V
REF
regulation circuits have been described and used with memory devices and other semiconductor devices, problems caused by noise within the device and by fluctuations in power supplies remain. Furthermore, these problems seem to be accentuated in high speed memory devices and other semiconductor devices operating at ever lower voltages. Therefore, it is desirous to provide a V
REF
to a semiconductor device which is not as susceptible to power supply fluctuations or noise from the circuits in the semiconductor device.
BRIEF SUMMARY OF THE INVENTION
The present invention generally relates to a method and apparatus for improving reference voltage stability in semiconductor devices. More specifically, the invention involves the integration of a circuit using V
REF
as a reference to generate a constant voltage in a semiconductor device to actively drive a reference voltage (V
REF
) within the memory device. It is understood that, while the present invention may be incorporated with any semiconductor device having need for a V
REF
signal the present invention will be described in reference to memory device.
According to the present invention, a V
REF
signal is actively driven on a memory device by coupling an external V
REF
signal to a circuit capable of generating a constant voltage and active current drive which is integrated with the memory device. For example, employing the combination of an external V
REF
signal with a voltage follower, a V
REF
current source substantially close to a constant voltage may be driven within the memory device. Unlike the V
REF
generated by V
REF
generators incorporated with semiconductor devices of the prior art, the V
REF
created by the voltage follower circuit is not subject to fluctuations due to changes in the power supply voltage V
DD
of the memory device because V
REF
is driven by an independent, external input voltage. Likewise, the substantially constant voltage driven by the voltage follower reduces the effects of coupling in the memory device and eliminates V
REF
fluctuations caused by noise in the memory device. Furthermore, the active current drive capability of the voltage follower circuit allows quick responses to other signals coupling V
REF
or causing fluctuations in V
REF
.


REFERENCES:
patent: 4006400 (1977-02-01), Fett et al.
patent: 4110677 (1978-08-01), Boronkay et al.
patent: 4270090 (1981-05-01), Williams et al.
patent: 4399398 (1983-08-01), Wittlinger
patent: 4477736 (1984-10-01),

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