Active X-Y addressable type solid-state image sensor and...

Television – Camera – system and detail – Solid-state image sensor

Reexamination Certificate

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Details

C348S302000

Reexamination Certificate

active

06778213

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a solid-state image sensor and a method of operating the same, and more particularly to an active X-Y addressable type solid-state image sensor having compatibility with CMOS fabrication process and a method of operating the same.
2. Description of the Related Art
Conventional solid-state image sensors can be grouped into MOS type and CCD type in accordance with a transfer layer for transferring signal charges generated by photoelectric transfer. In particular, CCD type solid-state image sensor has been widely used for VTR integrally including a camera, a digital camera, a fax machine and so on, and is presently being developed for enhancement in performances.
Some of solid-state image sensors have compatibility with a process of fabricating CMOS transistor (hereinafter, such solid-state image sensors are referred to simply as “CMOS sensor”, since they are generally so called), as described in IEDM 93, 1993, pp. 583-586, or Nikkei Micro Device, Vol. 7, 1997, pp. 120-125. CMOS sensor has advantages that it can operate with a single power source such as a 5V or 3.3V cell with the result of low power consumption, that it can be fabricated in conventional CMOS fabrication process, namely, it has compatibility with CMOS fabrication process, and that peripheral circuits such as a signal processing circuit can be mounted on a common chip.
FIG. 1
is a cross-sectional view of a conventional CMOS sensor.
FIG. 2
illustrates a photoelectric transfer section of the conventional CMOS sensor illustrated in
FIG. 1
in which electric charges are being accumulated therein, and
FIG. 3
illustrates the same photoelectric transfer section from which the thus accumulated electric charges have been read out.
With reference to
FIG. 1
, the illustrated CMOS sensor is comprised of a p-type semiconductor substrate
102
to which a VSS voltage such as 0V is applied. The p-type semiconductor substrate
102
includes therein a n-type well layer
103
to which a VDD voltage such as 3.3V is applied in such a manner that the n-type well layer
103
is inversely biased relative to the p-type semiconductor substrate
102
, first and second p-type well layers
104
a
and
104
b
to both of which the VSS voltage is applied, a p+ semiconductor region
105
formed in the n-type well layer
103
, a first n+ semiconductor region
106
formed in the second p-type well layer
104
b
, and a second n+ semiconductor region
106
a
formed in the first p-type well layer
104
a.
Externally of the p-type semiconductor substrate
102
are formed a photo-gate
201
located above an exposed region of the p-type well layer
104
a
, a first MOSFET
202
connected to the photo-gate
201
for transmitting an output signal, a second MOSFET
203
formed above the p-type well layer
104
a
for resetting electric charges accumulated in a photoelectric transfer section, a third MOSFET
204
receiving electric charges from the second MOSFET
203
and acting as a source follower amplifier, a fourth MOSFET
205
having a source or drain region to which a source or drain region of the third MOSFET
204
is electrically connected, and acting as a horizontal selection switch, a fifth MOSFET
206
having a source or drain region to which a source or drain region of the fourth MOSFET
205
is electrically connected, and acting as a source follower amplifier and a load, a sixth MOSFET
207
having a source or drain to which a source and a drain of the fourth and fifth MOSFETs
205
and
206
are electrically connected, and transferring dark output, a seventh MOSFET
208
having a source or drain to which a source and a drain of the fourth and fifth MOSFETs
205
and
206
are electrically connected, and transferring bright output, a first capacitor
209
electrically connected to a source or drain of the sixth MOSFET
207
for accumulating dark output therein, a second capacitor
210
electrically connected to a source or drain of the seventh MOSFET
208
for accumulating bright output therein, an n-channel MOSFET
211
formed on an exposed region of the second p-type well region
104
b
, and a p-channel MOSFET
212
formed on an exposed region of the n-type well layer
103
.
In the CMOS sensor, the first p-type well layer
104
a
located below the photo-gate
201
act as a photoelectric transfer section.
An operation of CMOS sensor having the above-mentioned structure, illustrated in
FIG. 1
, is explained hereinbelow with reference to
FIGS. 1
to
3
.
First, a control pulse &phgr; PG which is to be applied to the photo-gate
201
is set to have a high level voltage in order to expand a depletion layer below the photo-gate
201
, that is, to deepen a potential below the photo-gate
201
. While signal charges are being accumulated, the second n+ semiconductor region
106
a
which will make a floating diffusion layer is fixed at a source voltage VDD in order to prevent blooming, by setting a control pulse &phgr; R which is to be applied to the second MOSFET
203
, to have a high level voltage.
When the p-type semiconductor substrate
102
receives a light, electrons and holes are generated in a region located below the photo-gate
201
. The thus generated electrons are accumulated in a depletion layer formed below the photo-gate
201
, and the thus generated holes discharged through the first p-type well layer
104
a.
As illustrated in
FIG. 2
, since there is formed a potential barrier
300
caused by the first MOSFET
202
between a depletion layer formed in the first p-type well layer
104
a
acting as a photoelectric transfer section and the second n+ semiconductor region
106
a
which will makes a floating diffusion layer, electrons are accumulated below the photo-gate
201
while electric charges are being accumulated.
Then, the control pulse &phgr; R which is to be applied to the second MOSFET
203
is set to have a low level voltage, and the control pulse &phgr; PG which is to be applied to the photo-gate
201
is set to have a low level voltage in order to narrow a depletion layer below the photo-gate
201
, that is, to shallow a potential below the photo-gate
201
.
As a result, as illustrated in
FIG. 3
, electrons having been accumulated below the photo-gate
201
are transferred to the floating diffusion layer
106
a
over the potential barrier
300
formed below the first MOSFET
202
. Thus, since electrons are wholly transferred to the floating diffusion layer
106
a
, after images and noises are not generated in the photoelectric transfer section or first p-type well layer
104
a.
Then, a potential of the second n+ semiconductor region
106
a
is varied in accordance with the number of electrons having been transferred thereto. The variation in the potential of the second n+ semiconductor region
106
a
is output into the fourth MOSFET
205
acting as a horizontal selection switch through a source of the third MOSFET
204
acting as a source follower amplifier by virtue of source follower operation. Thus, there is obtained photoelectric transfer characteristic having superior linearity.
There is generated kTC noise caused by reset operation in the second n+ semiconductor region or floating diffusion layer
106
a
. However, such kTC noise can be removed by sampling and accumulating dark output generated prior to transfer of signal electric charges, and calculating a difference between bright output and the thus accumulated dark output.
However, the above-mentioned conventional solid-state image sensor having compatibility with CMOS fabrication process is accompanied with a problem as follows. In the above-mentioned conventional solid-state image sensor, the first p-type well layer
104
a
defining the photoelectric transfer section is formed in the semiconductor substrate
102
having the same electrical conductivity as that of the first p-type well layer
104
a
. Hence, there is high probability for floating electric charges to be absorbed into a potential well of the photoelectric transfer section
104

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