Active Vcc-to-Vss ESD clamp with hystersis for low supply chips

Details Active Vcc-to-Vss ESD clamp with hystersis for low supply chips Active Vcc-to-Vss ESD clamp with hystersis for low supply chips

2000-06-29

2003-04-22

Leja, Ronald W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

06552886

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor protection, and more particularly to electro-static-discharge (ESD) protection of core circuitry using dynamic circuits.
BACKGROUND OF THE INVENTION
Semiconductor process technology has produced extremely small transistors. These tiny transistors have thin oxide and insulating layers that can easily be damaged by relatively small currents with even a moderate driving force (voltage). Special care is required when a person handles these semiconductor devices.
Static electricity that normally builds up on a person can discharge across the input pins or a semiconductor integrated circuit (IC or chip). IC chips are routinely tested for resistance to such electro-static-discharges (ESD) using automated testers that apply a voltage across different pairs of pins of the chip. Any pair of pins may be chosen for the ESD test.
While input and output pins were originally provided with ESD-protection circuits, the core circuitry was directly connected to the Vcc power supply and the Vss ground supply. When an ESD pulse was applied between Vcc and Vss, little or no damage was apparent. The large number of transistors connected to the power and ground supplies apparently reduced the current surge in any one device, thus dissipating the ESD pulse using the chip's internal transistors.
However, as device sizes continued to shrink, damage began occurring when ESD pulses were applied between power and ground. The exact failure mechanism could be difficult to determine, and varied from design to design with the circuit and geometry of the integrated circuit (IC). ESD-protection circuits then were provided for power-supply pins. One kind of IC that is sensitive to Vcc-to-Vss ESD pulses is a mixed-signal chip that has several different power supplies. See the related co-pending application for an “Actively-Driven Thin-Oxide MOS Transistor Shunt for ESD Protection of Multiple Independent Supply Busses in a Mixed-Signal Chip” assigned to Pericom Semiconductor, Ser. No. 09/251,722, filed Feb. 17, 1999. However, even single-supply chips can benefit from Vcc-to-Vss protection circuits.
FIG. 1A
shows a simplified prior-art ESD protection device using a thick-oxide transistor. Power-supply Vcc and ground Vss are connected by thick-oxide transistor
10
, which does not normally conduct so that the supplies are isolated. However, when a high voltage is applied across Vcc and Vss during an ESD event, thick-oxide transistor
10
conducts, either by the high voltage forming a conducting channel under the thick field-oxide under the gate, or by punch-through in the substrate from drain to source in the substrate. Thus core circuitry
12
is protected when thick oxide transistor
10
turns on.
While such thick-oxide transistors are less sensitive to damage than thin-oxide transistors, the amount of current conducted is reduced. A very high gate voltage is needed to turn on the transistor since the channel is separated from the gate by the larger distance of the thick oxide. Damage to other thin-oxide transistors on the chip can occur before the thick-oxide transistor turns on. Thus the protection provided by thick-oxide transistor
10
is less than desired.
FIG. 1B
shows a thin-oxide transistor ESD-protection device. Core circuitry
12
is protected by n-channel transistor
14
, which uses the same thin oxide as other transistors in core circuitry
12
. Since the gate of n-channel transistor
14
is grounded, it does not turn on by channel formation in the normal manner. Instead, when a high voltage is applied across its source and drain terminals, the lateral NPN transistor turns on.
FIG. 1C
shows a snapback I-V curve for the n-channel transistor of FIG.
1
B. When a high voltage is applied, the n-channel transistor turns on, reducing the source-drain voltage while conducting a large current.
FIG. 2
shows the lateral NPN transistors in n-channel transistor
14
.
A large base-emitter area is required to conduct enough current. A width of 400 microns may be required for transistor
14
. Also, if one of the transistors in core circuitry
12
turns on its parasitic lateral transistor before transistor
14
, then core circuitry
12
is subjected to the ESD current stress rather than n-channel transistor
14
.
FIG. 3
shows an active clamp with an R-C sense for ESD protection. Rather than use passive circuits, such as the simple transistors of
FIGS. 1A
,
1
B, a more complex active circuit can be used to sense the ESD pulse and turn on the clamp transistor. See for example, “Basic ESD and I/O Design” by Dabral and Maloney, pages 61-62.
Core circuitry
12
is protected by clamp transistor
22
, which has its gate actively driven by inverter string
20
. An R-C sensing element is formed by capacitor
18
and transistor
16
, which is a grounded-gate p-channel transistor.
While such an active ESD-protection circuit is useful, it may be susceptible to noise, especially during power-up of the chip. If the active ESD-protection circuit triggers during power-up, excessive current may be drawn through the clamp transistor, resulting in a drop in Vcc or even Latch-up. Low-voltage supplies may be more susceptible since the Vcc ramp is shallower.
What is desired is an ESD-protection circuit that protects the internal power supplies of an IC. An active rather than a passive protection circuit is desired. It is desired to actively enable or disable the ESD-protection circuit. It is desired to actively enable and disable a thin-oxide transistor as an ESD shunt between power and ground busses. It is desired to avoid thick-oxide transistors and diodes. An active ESD-protection circuit that is insensitive to noise during power up is desired.
SUMMARY OF THE INVENTION
A protection circuit has a clamping transistor that is coupled to shunt current from an electro-static-discharge (ESD) pulse. It has a control gate. A voltage divider is coupled to the ESD pulse. It generates a divided voltage that is a predetermined fraction of a voltage of the ESD pulse. A chain of inverters receives the divided voltage. They drive the control gate of the clamping transistor.
An extending transistor drives an extended internal node in the chain of inverters. It has a gate that receives a feedback voltage from another internal node in the chain of inverters after the extended internal node. Thus the extending transistor extends a discharge time that the clamping transistor is shunting current during the ESD pulse.
In further aspects a hysteresis transistor is coupled to drive an output of an inverter in the chain of inverters. It increases a divided voltage required to turn on the control gate of the clamping transistor. Thus a higher turn-on voltage is required.
In further aspects the hysteresis transistor is a transistor that couples a first internal node in the chain of inverters to a power supply. The hysteresis transistor has a gate coupled to a second internal node after the first internal node. The second internal node is driven by an inverter that has the first internal node as an input. Thus hysteresis is provided by coupling to the power supply.
In other aspects the hysteresis transistor is a p-channel transistor while the clamping transistor is an n-channel transistor.
In further aspects the clamping transistor has a drain coupled to a power supply, and a source coupled to a ground. Thus the clamping transistor shunts current from power to ground when the ESD pulse is applied from a power pin to a ground pin. The extending transistor is an n-channel transistor coupled between the extended internal node and the ground. The extending transistor has a gate coupled to the control gate of the clamping transistor. Thus the extending transistor and the clamping transistor share a common gate node.
In still further aspects the chain of inverters includes a first inverter that receives the divided voltage from the voltage divider to output the first internal node, a second inverter that receives the first internal node and outputs the second internal node, a third inverter tha

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