Television – Camera – system and detail – Solid-state image sensor
Reexamination Certificate
2000-02-01
2004-08-31
Garber, Wendy R. (Department: 2612)
Television
Camera, system and detail
Solid-state image sensor
C250S208100, C257S291000
Reexamination Certificate
active
06784934
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit technology for reducing the pixel leak current of an active type solid-state imaging device.
2. Description of the Related Art
Various active type solid-state imaging devices have been proposed in the art in which each pixel is provided with an amplification function, and a scanning circuit is used to read a signal amplified by the pixel. One of such active type solid-state imaging devices is an APS (Active Pixel Sensor) type image sensor which employs a CMOS device for each pixel. The use of a CMOS device is advantageous in integrating the pixel configuration with the peripheral units such as a driving circuit and a signal processing circuit. An APS typed image sensor requires a photoelectric conversion section, an amplification section, a pixel selection section, and a reset section to be provided in each pixel. Thus, an APS type image sensor typically uses, for each pixel, one photoelectric conversion section formed of a photo diode (PD) and three or four MOS transistors (T).
FIG. 5
shows a configuration of a two-dimensional area image sensor employing the conventional PD+3T pixel configuration (Mabuchi, et. al., “A ¼ Inch 330 k Pixel VGA CMOS Image Sensor”, The Technical Report of Institute of Image Information and Television Engineers, IPU97-13, March, 1997).
Referring to
FIG. 5
, each pixel includes a photoelectric conversion photo diode
5
, an amplification MOS transistor
1
, a reset MOS transistor
2
, a pixel selection MOS transistor
3
, a pixel selection clock line
11
, a reset clock line
12
, a signal line
13
and a power source line
14
.
The MOS transistor
3
is driven by a vertical scanning circuit (I)
20
through the pixel selection clock line
11
, and the MOS transistor
2
is driven by another vertical scanning circuit (II)
21
through the reset clock line
12
. A MOS transistor
15
(the gate bias voltage is shown as V
L1
) is connected to the signal line
13
as a load for supplying a constant current. The output voltage of the MOS transistor
15
is eventually passed to a horizontal signal line
19
through an amplifier (an amplification MOS transistor)
16
and a MOS transistor
17
. The MOS transistor
17
is driven by a horizontal scanning circuit
22
through a horizontal clock line
18
. A MOS transistor
23
(the gate bias voltage is shown as V
L2
) is connected to the horizontal signal line
19
as a load for supplying a constant current. The output voltage of the horizontal signal line
19
is led to an output terminal OS through an amplifier
24
.
In
FIG. 5
, the MOS transistors
1
,
2
, and
3
are all n-type enhancement MOS transistors, and the photo diode
5
is a pn junction diode. With this configuration, it is easy to form the pixels by an ordinary CMOS process. The peripheral circuits (including the analog circuits such as the amplifiers
16
and
24
and the digital circuits such as the vertical scanning circuits
20
and
21
and the horizontal scanning circuit
22
) are typically CMOS circuits. Therefore, it is possible to form both the pixels and the peripheral circuits in a common process. Thus, the pixels and the periphery circuits can be commonly connected to a single power source (e.g., V
D
).
In the configuration shown in
FIG. 5
, all the transistors
1
,
2
, and
3
are n-type enhancement MOS transistors. Therefore, the input/output characteristic of a source follower circuit which includes the amplification MOS transistor
1
and the MOS transistor
15
as a load for supplying a constant current will be as shown in FIG.
6
. In
FIG. 6
, V
T1
is the threshold voltage of the amplification MOS transistor
1
, V
T2
is the threshold voltage of the MOS transistor
15
as a load for supplying a constant current, and V
L
is the gate bias voltage of the MOS transistor
15
. For an output voltage v
o
within the range:
v
o
>V
L
−V
T2
,
the MOS transistor
15
as a load for supplying a constant current is saturated, thus ensuring linearity of the input/output relationship. Therefore, a sufficient operational margin cannot be obtained unless the input voltage v
i
is at a high level near the source voltage V
D
.
In the configuration shown in
FIG. 5
, the pn junction diode forming the photoelectric conversion photo diode
5
is reversely biased to the magnitude of the voltage V
D
by resetting the photo diode
5
to the magnitude of the source voltage V
D
. A leak current may occur in the pn junction diode due to the reverse bias. In such a case, the leak current is accumulated during each photo carrier charging period and added to the signal charge, thus generating a false signal. The amount of the leak current varies among different pixels, thereby causing fixed-pattern noise in the displayed image. A localized leak current may generate a white defect. Therefore, the leak current may significantly degrade the image quality.
The amount of leak current generated in the pn junction diode is strongly dependent on the magnitude of the reverse bias voltage, and rapidly increases as shown in
FIG. 7
as the reverse bias voltage increases. Therefore, it is necessary to reduce the reverse bias voltage, and hence the source voltage, in order to reduce the amount of leak current generated in the pn junction diode. This, however, leads to the reduction of the operational margin as shown in FIG.
6
. The trade-off relationship has been a significant problem in APS type CMOS image sensors.
SUMMARY OF THE INVENTION
According to one aspect of this invention, an active type solid-state imaging device includes: a plurality of pixels arranged in an array; a plurality of signal lines wherein each of the pixels is connected to one of the signal lines; a first power source; and a second power source having a lower voltage than that of the first power source. Each of the pixels includes: a photoelectric conversion section; a first, depletion type MOS transistor: a second, reset MOS transistor for resetting a signal charge which has been stored in the photoelectric conversion section; and a third, pixel selection MOS transistor serially connected to the first MOS transistor to form a transistor pair. One end of the transistor pair is connected to one of the signal lines and the other end thereof is connected to the first power source. One end of the second MOS transistor is connected to the photoelectric conversion section and the other end thereof is connected to the second power source.
In one embodiment of the invention, the second MOS transistor and the third MOS transistor are of a depletion type.
In one embodiment of the invention, each of the signal lines is connected to a signal processing circuit driven by the first power source.
In one embodiment of the invention, the second power source includes the first power source and a voltage dividing circuit for dividing the voltage of the first power source.
In one embodiment of the invention, the voltage dividing circuit includes a voltage follower circuit.
In one embodiment of the invention, the voltage dividing circuit includes a circuit having one or more diodes connected together in a forward direction.
In the active type solid-state imaging device according to the present invention, the reverse bias voltage applied to the pn junction diode as a light detecting section is set to be lower than the source voltage which is necessary for signal reading operations. Therefore, the amount of leak current generated in the light detecting section is greatly reduced. Furthermore, according to the present invention, by using a depletion type transistor for a signal amplification MOS transistor, a sufficient operational margin is ensured even if the reverse biased voltage applied to the pn junction diode is low.
Thus, the invention described herein makes possible the advantage of providing a novel active type solid-state imaging device having a very simple configuration in which the amount of leak current generated in a pn junction diode is reduced and a sufficient operational margi
Edwards & Angell LLP
Garber Wendy R.
Sharp Kabushiki Kaisha
Tucker David A.
Villecco John M.
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