Active terminate command in synchronous flash memory

Details Active terminate command in synchronous flash memory Active terminate command in synchronous flash memory

2000-06-30

2001-08-21

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Byte or page addressing

C365S185330

Reexamination Certificate

active

06278654

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to non-volatile memory devices and in particular the present invention relates to a synchronous non-volatile flash memory.
BACKGROUND OF THE INVENTION
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory. One type is RAM (random-access memory). This is typically used as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modern PCS have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in modems because it enables the modem manufacturer to support new protocols as they become standardized.
A typical Flash memory comprises a memory array which includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU's bus and is capable of running at 100 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. SDRAM's can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a non-volatile memory device that can operate in a manner similar to SDRAM operation.
SUMMARY OF THE INVENTION
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a synchronous flash memory device comprises an array of non-volatile memory cells arranged in banks of rows and columns, address connections to receive address signals, and a clock connection to receive an external clock signal. The memory further comprises a chip select (CS#) connection to receive a chip select signal, a row address strobe (RAS#) connection to receive a row address strobe, a column address strobe (CAS#) connection to receive a column address strobe, and a write enable (WE#) connection to receive a write enable signal. Control circuitry is included to perform a burst read operation of memory cells in a first block of the array and interrupt the burst read operation when the chip select signal is active, the row address strobe is either inactive or active, the column address strobe is de-active, the write enable signal is active, and the address signals identify the first block simultaneously during the burst read operation.
In another embodiment, a synchronous flash memory device comprises an array of non-volatile memory cells arranged in banks of rows and columns, address connections to receive address signals, and control connections to receive control signals. The control connections comprise a clock connection to receive an external clock signal, a chip select (CS#) connection to receive a chip select signal, a row address strobe (RAS#) connection to receive a row address strobe, a column address strobe (CAS#) connection to receive a column address strobe, and a write enable (WE#) connection to receive a write enable signal. Control circuitry is included to perform a burst read operation of memory cells in a first block of the array and interrupt the burst read operation when the control signals are in a predetermined combination and the address signals identify the first block simultaneously during the burst read operation.
A method of terminating a read operation in a synchronous flash memory device is provided. The method comprises initiating a burst read operation to output data from a plurality of non-volatile memory cells located in different columns of the synchronous flash memory device, and receiving an externally provided active terminate command. The active terminate command comprises an active chip select signal, an active row address strobe signal, a de-active column address strobe signal, and an active write enable signal. The method further comprises terminating the burst read operation in response to the burst terminate command.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A
is a block diagram of a synchronous flash memory of the present invention;
FIG. 1B
is an integrated circuit pin interconnect diagram of one embodiment of the present invention;
FIG. 1C
is an integrated circuit interconnect bump grid array diagram of one embodiment of the present invention;
FIG. 2
illustrates a mode register of one embodiment of the present invention;
FIG. 3
illustrates read operations having a CAS latency of one, two and three clock cycles;
FIG. 4
illustrates activating a specific row in a bank of the memory of one embodiment of the present invention;
FIG. 5
illustrates timing between an active command and a read or write command;
FIG. 6
illustrates a read command;
FIG. 7
, illustrates timing for consecutive read bursts of one embodiment of the present invention;
FIG. 8
illustrates random read accesses within a page of one embodiment of the present invention;
FIG. 9
illustrates a read operation followed by a write operation;
FIG. 10
illustrates read burst operation that are terminated using a burst terminate command according to one embodiment of the present invention;
FIG. 11
illustrates a write command;
FIG. 12
illustrates a write followed by a read operation;
FIG. 13
illustrates a power-down operation of one embodiment of the present invention;
FIG. 14
illustrates a clock suspend operation during a burst read;
FIG. 15
illustrates a memory address map of one embodiment of the memory having two boot sectors;
FIG. 16
is a flow chart of a self-timed write sequence according to one embodiment of the present invention;
FIG. 17
is a flow chart of a complete write status-check sequence according to one embodiment of the present invention;
FIG. 18
is a flow chart of a self-timed block erase sequence according to one embodiment of the present invention;
FIG. 19
is a flow chart of a complete block erase status-check sequence according

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