Active surge rejection circuit

Details Active surge rejection circuit Active surge rejection circuit

1993-06-09

1994-05-24

Dwyer, James L.

Telephonic communications

Subscriber line or transmission line interface

Protective circuit

379399, 361 56, 361 91, 361111, 375 8, H02H 300, H02H 322, H02H 904, H04M 900

Patent

active

053156510

ABSTRACT:
The ACTIVE SURGE REJECTION CIRCUIT uses a FET connected in one of the TIP and RING leads to open and close the lead. A JK flip-flop is connected to a voltage sensing circuit which senses voltage surges and clocks the flip-flop early in the voltage rise. This activates a first circuit to ground the FET gate and hold the FET open. Meanwhile, a second circuit comprising an RC circuit charges a capacitor which maintains the FET in its OFF condition for a period of time longer than the surge, i.e., about 1 m sec, and then clears the JK flip-flop after the capacitor has discharged a predetermined amount. This invention thus provides surge (noncommon mode) protection, and is especially useful in protecting modems from voltage surges while minimizing signal distortion during non-surge conditions.

REFERENCES:
patent: 4079211 (1978-03-01), Janssen
patent: 4398066 (1983-08-01), Sinberg
patent: 4433212 (1984-02-01), Moses et al.
patent: 4465903 (1984-08-01), Barber
patent: 4718084 (1988-01-01), Dragotin
patent: 5130883 (1992-07-01), Edwards
patent: 5208718 (1993-05-01), Fox
"Radio Shack New 1974-75 Dictionary of Electronics" Rudolf F. Graf pp. 28, 145, 155,373,374, and 687.

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