Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2000-09-18
2002-12-03
Patel, Rajnikant B. (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
C363S046000
Reexamination Certificate
active
06489755
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to communication circuits and components, and is particularly directed to a new and improved active noise (ripple) filter circuit, that is operative to effectively reduce or cancel unwanted, relatively low frequency AC component variations (such as a 20 Hz ringing voltage signal) riding on a DC voltage supplied over (tip/ring) wireline conductors to a load such as, but not limited to, a subscriber line interface circuit (SLIC).
BACKGROUND OF THE INVENTION
As a result of continuing improvements to and miniaturization of telecommunication equipment and components therefor, unwanted variations (e.g. noise and ripple) on the voltage supply rails powering various signaling components has increased. As a non-limiting example, a significant reduction in size and improvement in the efficiency of circuitry employed to ring a POTS (plain old telephone service) line can be attained by using a four-quadrant ringing signal generator, which recycles energy back to the −48V supply, rather than simply dissipating that energy (in the form of heat). Unfortunately, this energy recovery process causes modulation of the (−48V) DC voltage supply rails at frequencies down to less than a few Hertz (depending upon ringing frequency, cadence, and sequencing). Since the DC power source also supplies power to one or more SLICs, ripple can cause compatibility problems with some devices.
For example, the circuitry configurations of relatively inexpensive, low end SLICs are not able to adequately attenuate excessive ripple, so that some amount of ripple will still be transmitted to the POTS loop. In addition, ripple on tip and ring can prevent inexpensive Caller-ID devices from receiving on-hook data transmissions. Although filtering ripple and noise using passive components, such as resistors, capacitors and inductors, would appear to be a logical answer, it is impractical due to the very low frequencies involved.
Another potentially viable solution to ripple cancellation is to use a linear voltage regulator. However, to be employable in most telecommunication industry applications, a linear voltage regulator would be required to operate at up to −70 VDC and, as a result of thermal considerations, would have to track the input, rather than providing a prescribed reference voltage. For example, the range of a −48 VDC supply is typically on the order of −40 VDC to −56 VDC, depending on the battery state of charge. In addition, a linear voltage regulator must be provided with some amount of voltage rail ‘headroom’, in order to be able to attenuate the ripple. In some cases, even a low dropout regulator would require on the order of one volt of headroom due to excessive amounts of ripple. As a result, a fixed regulator would typically be adjusted to provide −39 VDC. Although this regulated voltage is sufficient for the input voltage range, at a high line voltage power dissipation would be unacceptable (on the order of twelve watts), since the loop current required by multiple (e.g., 24) POTS lines can exceed 700 mA.
SUMMARY OF THE INVENTION
In accordance with the present invention, the problem of low frequency ripple noise riding on a DC voltage to be delivered to a load is effectively obviated without the attendant shortcomings of strictly passive or voltage regulator solutions, discussed above, by an active tracking filter that is operative to sense the average value of low frequency variation of the DC voltage, and then controllably reduce that average voltage value by a voltage drop that is sufficient to accommodate the maximum amplitude of the unwanted AC (ripple) component.
Pursuant to a non-limiting application example of a telecommunication circuit application of the invention, the DC voltage may be supplied from an upstream (e,.g., central office-resident) DC voltage source to respective tip and ring conductors of a telecommunication wireline pair, by means of one or more subscriber line interface circuits (SLICs). A low frequency voltage average detector circuit (such as a low pass filter) is coupled across the power input conductors upstream of the SLIC(s). This detector supplies an output voltage representative of the average value of the low frequency composite voltage (DC source voltage plus ripple) on the wireline pair to a first input of an error amplifier of a ripple voltage cancellation circuit that is coupled between the DC voltage source and the load (SLIC). The error amplifier has a second input coupled to receive the output voltage produced by an output voltage sensor coupled across the power input conductors feeding the SLIC(s).
The output of the error amplifier is coupled to the control terminal of a controlled impedance installed in the current flow path of one of the conductors of the DC source. As a non-limiting example, the controlled impedance may comprise a controllable semiconductor device, such as a field effect transistor (FET), having its source-drain path installed in the wireline path of interest. The FET is biased to operate in its linear range, and produces a controlled drain-source voltage drop thereacross in proportion to applied gate voltage.
The parameters of the circuit are defined such that the value of the controlled voltage drop across the FET accommodates the maximum amplitude of the unwanted AC/ripple component of the DC voltage. Namely, the error amplifier controls the FET, such that the output voltage applied from its downstream end effectively corresponds to the average value of the low frequency DC voltage sensed by the average detector, minus a small offset or ‘headroom’ voltage associated with and attenuating the ripple.
Each of the average detector and output voltage sensor includes a respective resistor-configured voltage divider to scale down the input and output voltages. In a practical circuit, by appropriate choice of the values of the voltage divider resistors, the adjusted output voltage at the output of the controlled FET may be set at a value that is slightly less than the low frequency average value of the input voltage. For an average input voltage value on the order −40V, the resulting output voltage may be on the order of −39V, which provides sufficient headroom for attenuating unwanted AC ripple under normal operating conditions.
Because of the high voltages involved in telecommunication wireline applications, implementing the error amplifier with a standard operational amplifier would mandate the use of a relatively cumbersome powering circuit. This potential problem is readily obviated by employing discrete components to emulate the function of an operational amplifier. The error amplifier may be configured of a differentially coupled pair of bipolar transistors, which controllably steer an emitter coupled bias current to either the gate of the FET or to the FET's output terminal. When the output voltage increases incrementally, the current is steered so as to increase the gate-source voltage of the FET and thereby increase the conductivity of the FET. As a result, its output voltage is reduced. Conversely, when the value of the output voltage is incrementally decreased, the current is steered so as to decrease the gate-source voltage of the FET and thereby reduce its conductivity, and increase the output voltage.
Protection diodes may be incorporated into the error amplifier to protect the base-emitter junctions of its differentially coupled transistor pair during power-up and transients. A protection diode may be coupled with the low pass filter circuit to reset the filter capacitor during anomalies in the power supply voltage or power cycling. To protect the FET gate during transients, a Zener diode may be coupled across its gate and source.
Current limiting protection may also be provided by installing a supply current sense resistor in the wireline path through the FET. An additional by-pass transistor may be connected with its base-emitter terminals coupled across the sense resistor, and its collector coupled to
Boudreaux, Jr. Ralph R.
McGary John S.
Robinson Steven M.
Adtran Inc.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Patel Rajnikant B.
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