Active reset forward converter employing synchronous rectifiers

Details Active reset forward converter employing synchronous rectifiers Active reset forward converter employing synchronous rectifiers

2000-05-15

2001-06-26

Patel, Rajnikant B. (Department: 2838)

Electric power conversion systems

Current conversion

Including d.c.-a.c.-d.c. converter

C363S017000, C363S020000

Reexamination Certificate

active

06252781

ABSTRACT:

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
This invention pertains to active reset forward converters employing synchronous rectifiers.
Carsten, “High Power SMPS Require Intrinsic Reliability,” PCI Proceedings, Sep. 14, 1981, pp. 495-501, describes a single-ended forward converter comprising a reset circuit sometimes referred to as an “active clamp.” The active clamp comprises a capacitor and switch coupled to a power transformer for resetting the transformer and preventing saturation. A similar circuit is discussed by Carsten in “Design Tricks, Techniques and Tribulations at High Conversion Frequencies”, HFPC, April 1987, pp. 139-152, and “Techniques for Transformer Active Reset Circuits at High Frequencies and Power Levels”, HFPC, May 1990, pp. 235-246. The Carsten articles are incorporated herein by reference.
The Carsten circuits employ an output filter circuit comprising diodes for receiving an AC voltage from the transformer secondary winding and generating therefrom a DC output voltage. It is known in the art to replace such diodes with MOSFETs, e.g. as described by James Blanc in “Practical Application of MOSFET Synchronous Rectifiers,” published at the Intelec '91 conference, incorporated herein by reference.
FIG. 1
illustrates a prior art circuit including a reset circuit combined with synchronous rectifiers.
FIG. 1
includes a DC input voltage source
1
. A main power switch
2
periodically turns on and off for coupling the DC input voltage across a primary winding
3
of an isolation transformer
4
. A reset switch
5
and a capacitor
6
are included in this circuit. When main power switch
2
is off, switch
5
is closed, thereby coupling the series combination of capacitor
6
and input voltage source
1
across winding
3
. Capacitor
6
typically stores a DC voltage such that the sum of the DC voltage on capacitor
6
plus the DC input voltage from supply
1
is sufficient to reset transformer
4
when switch
5
is closed. Thus, when switch
2
is closed, a positive DC input voltage is applied across primary winding
3
, and when switch
5
is closed, a negative DC voltage (equal to the input voltage plus the voltage across capacitor
6
) is applied across winding
3
to reset transformer
4
.
Transformer
4
includes a secondary winding
7
coupled to a filter/rectifier circuit
8
. Filter/rectifier circuit
8
includes synchronous rectifiers
9
and
10
, an inductor
11
and a capacitor
12
. Circuit
8
receives an output voltage waveform from secondary winding
7
and generates in response thereto a DC output voltage across output leads
13
,
14
. Synchronous rectifiers
9
,
10
are MOS transistors, including parasitic diodes
9
d
,
10
d
coupled across their source and drain.
When switch
2
is closed, a positive voltage is present across winding
3
, thereby causing a positive voltage across winding
7
, which turns on synchronous rectifier
9
and turns off synchronous rectifier
10
. When switch
5
is closed, a negative voltage is present across winding
3
, thereby causing a negative voltage across winding
7
, which turns off synchronous rectifier
9
and turns on synchronous rectifier
10
. The advantage of using synchronous rectifiers
9
,
10
instead of diodes is that the voltage drop across rectifiers
9
,
10
is less than the voltage drop across a typical diode (0.7 volts), and therefore, efficiency of this circuit is enhanced.
FIGS. 2A and 2B
illustrate the gate voltage applied to MOS switches
2
and
5
, respectively. As can be seen, these gate voltages are out of phase.
FIG. 2C
illustrates the voltage vp across winding
3
caused by transistors
2
and
5
turning on and off.
Unfortunately, the gates
9
g,
10
g
of MOS synchronous rectifiers
9
,
10
are typically very capacitive.
FIGS. 2D and 2E
illustrate the voltage applied to gates
9
g,
10
g
of synchronous rectifiers
9
,
10
by secondary winding
7
. As can be seen, here is a small time period in which the voltages at gates
9
g,
10
g
are both high, thereby causing a small time period during which both rectifiers
9
,
10
conduct, which in turn causes large current pulses P
1
, P
2
to flow through rectifiers
9
,
10
when rectifiers
9
,
10
are both conducting. (The current through rectifier
9
is illustrated in
FIG. 2F.
) It would be desirable to eliminate these large current pulses.
SUMMARY
A circuit constructed in accordance with our invention comprises a main power switch for coupling an input voltage source to a primary winding of a transformer and a reset switch for coupling a reset voltage source to the primary winding. In one embodiment, the reset voltage source is a capacitor for storing a reset voltage. The circuit also comprises first and second synchronous rectifiers. One of the synchronous rectifiers acts as a freewheeling diode. The other synchronous rectifier selectively couples the secondary winding to an output filter circuit. The synchronous rectifiers are controlled by the transformer. A control circuit controls the main power switch and the reset switch. The control circuit comprises a delay circuit for providing a delay between the time the input switch opens and the reset switch closes, and a delay between the time the reset switch opens and the input switch closes. In accordance with one novel feature of our invention, this delay is sufficiently long to ensure that there is no time period during which both synchronous rectifiers are conducting.


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Murakami, et al., “A Simple and Efficient Synchronous Rectifier for Forward DC-DC Converters”, Apec '93, Eighth Annual Applied Power Electronics Conference and Exposition, pp. 463-468, Mar. 7-11, 1993.
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