Active pull-up circuit

Details Active pull-up circuit Active pull-up circuit

1999-04-30

2002-03-26

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S309000, C327S321000, C326S082000, C326S087000

Reexamination Certificate

active

06362664

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior Italian Patent Application No. TO-98-A000373, filed Apr. 30, 1998, the entire disclosure of which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electronic circuits, and more specifically to an active pull-up circuit for an input that can receive a voltage that is higher than the supply voltage.
2. Description of Related Art
Conventional electronic circuits and integrated circuits have a certain number of input terminals or pins that can be used to make electric connections to transfer signals from the external environment to the circuit. The signals are typically logic signals with two voltage levels (e.g., 0 and 5 volts) and the input pin can have three different statuses: 0 volts, 5 volts, and a floating voltage (i.e., equivalent to the pin not being connected). With respect to the floating voltage status, in order to avoid an unpredictable status of the circuit, a pull-up function is usually implemented on the pin through a special circuit to quickly bring the voltage on the pin to the supply voltage (i.e., the high logic level V
5
of 5 volts) when the input pin is disconnected and the voltage level is floating.
FIG. 1
shows an example of a conventional input circuit
1
that is formed using CMOS technology. As shown, an input pin IN supplies an input signal to a buffer circuit
2
that supplies an output signal to an output pin OUT. The buffer circuit
2
performs the usual separation functions of the voltage levels on the output pin OUT from the levels present on the input pin IN. A 5 volt voltage supply line VDD is connected to one of the supply pins
2
VDD of the buffer circuit
2
, and a ground node GND is connected to the other supply pin
2
VDD. An active pull-up circuit PU is located between the input pin IN and the voltage supply line VDD.
The active pull-up circuit PU has a conventional current mirror circuit MR from which a current IP is drawn through a current generator I. The current mirror MR has two transistors: a P-channel injection transistor M
2
with its gate electrode short-circuited with the drain electrode and a P-channel mirror transistor M
1
connected through its gate electrode to the gate electrode of the injection transistor M
2
. The current IP is mirrored by the current mirror MR and injected into the input pin node IN. When a floating voltage level is present on the input pin IN (e.g., the input pin IN is disconnected), the current mirror MR brings the input pin IN to the level of the supply voltage.
Conventional active pull-up circuits such as the active pull-up circuit PU of
FIG. 1
present some drawbacks when, in addition to the logic levels used by the circuit, a higher voltage (e.g., 15 volts) needs to be applied in order to communicate with downstream circuitry. For example, although downstream circuits may also operate during normal operation steps according to standard TTL logic levels (i.e., between 0 and 5 volts), the downstream circuits may include EPROM memory circuits that have a particular operation step of their own (e.g., a programming operation step) that requires a higher voltage such as 15 volts to be produced on their gate electrodes.
However, when such a 15 volt level is applied to the input pin, the mirror transistor M
1
has a voltage of 15 volts on its drain electrode and 5 volts on its source electrode, so its drain-substrate junction is directly biased. Therefore, the mirror transistor enters a conduction state, and the 5 volt supply voltage and the 15 volt input voltage from the input pin have a conflict that can damage the circuits connected to the voltage supply line.
SUMMARY OF THE INVENTION
In view of these drawbacks, it is an object of the present invention to overcome the above-mentioned drawbacks and to provide an active pull-up circuit that has a more efficient and improved performance.
Another object of the present invention is to provide an active pull-up circuit that avoids a conflict between the supply voltage and the input voltage when the input voltage is higher than the supply voltage.
One embodiment of the present invention provides an active pull-up circuit for connection to an input pin that receives high and low logic level signals and a high voltage signal whose level is higher than the high logic level. The active pull-up circuit includes a pull-up circuit that is coupled between the input pin and a voltage supply line, and a breaking circuit that is coupled between the pull-up circuit and the voltage supply line. The pull-up circuit selectively brings the input pin to the level of the voltage supply line, and the breaking circuit operates to inhibit the pull-up circuit when the high voltage signal is on the input pin. In a preferred embodiment, the breaking circuit inhibits the pull-up circuit by electrically isolating the pull-up circuit from the voltage supply line.
Another embodiment of the present invention provides a method for selectively pulling-up an input node of a circuit that receives a supply voltage. According to the method, the input node is pulled-up to the level of the supply voltage at least when the input node receives a floating voltage, and such pulling-up of the input node is inhibited at least when the input node receives a high voltage signal whose level is higher than the level of the supply voltage. In one preferred method, either the pulling-up operation or the inhibiting of the pulling-up operation is performed based on the level on the input node.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.


REFERENCES:
patent: 4628218 (1986-12-01), Nakaizumi
patent: 5367210 (1994-11-01), Lipp
patent: 5489861 (1996-02-01), Seymour
patent: 5617051 (1997-04-01), Bingham
patent: 5952875 (1999-09-01), Yosefin et al.

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