Active pull-up circuit

Details Active pull-up circuit Active pull-up circuit

1982-09-24

1985-03-05

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 307443, 307453, 307578, 365203, G11C 700, H03K 505, H03K 17693

Patent

active

045033439

ABSTRACT:
Provided is an active pull-up circuit which comprises a MOS capacitor having one end connected to an input terminal receiving a pull-up signal, a first MOS transistor having a current path connected between the other end of said MOS capacitor and a signal line precharged, during a precharge period, up to a power source voltage level, and a second MOS transistor having a current path connected between a power source terminal and the signal line and having a gate connected to a source of the first MOS transistor. To the gate of this first MOS transistor there is applied a control voltage which, during the precharge period, is higher in level than a sum of the power source voltage and a threshold voltage of the first MOS transistor and, after the lapse of the precharge period, is substantially equal in level to the power source voltage.

REFERENCES:
patent: 4347448 (1982-08-01), Plachno
patent: 4352996 (1982-10-01), White, Jr.
patent: 4398100 (1983-08-01), Tobita et al.
patent: 4417329 (1983-11-01), Mezawa et al.
Arzubi, "High-Speed, Low-Power Inverter", IBM Tech. Disc. Bull., vol. 17, No. 10, Mar. 1975, p. 2834.
ISCC Digests of Technical Papers, 1979, p. 144-145, A 5V-only 2Kx8 Dynamic RAM by S. S. Eaton.

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