Active pixel sensor with switched supply row select

Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit

Reexamination Certificate

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C257S291000, C348S308000

Reexamination Certificate

active

06323476

ABSTRACT:

FIELD OF INVENTION
This invention relates to the field of solid state photo-sensors, and more specifically to imagers referred to as active pixel sensors (APS).
BACKGROUND OF THE INVENTION
APS are solid state imagers where each pixel contains a photo-sensing means, reset means, charge to voltage conversion means, and all or part of an amplifier. APS devices have been operated in a manner where each line or row of the imager is selected and then read out using a column select signal (analogous to a word and bit line in memory devices respectively). The row select operation has been accomplished in prior art devices by incorporation of a row select transistor in each pixel that is turned on to make that row active (see FIG.
1
). Since this transistor is placed in each pixel, its inclusion reduces the fill factor for the pixel because it takes up area that could otherwise be used for the photodetector, or charge storage region. This reduces the sensitivity and saturation signal of the sensor.
In order to build high resolution, small pixel APS devices, it is necessary to use sub-micron CMOS processes in order to minimize the area of the pixel allocated to the row select transistor and other parts of the amplifier in the pixel. In essence, it takes a more technologically advanced and more costly process to realize the same resolution and sensitivity APS device compared to a standard charge coupled device (CCD) sensor. However, APS devices have the advantages of single 5V supply operation, lower power consumption, x-y addressability, image windowing, and the ability to effectively integrate signal processing electronics on chip, when compared to CCD sensors.
One approach to providing an image sensor with the sensitivity of a CCD and the advantages of an APS device, is to improve the fill factor and sensitivity of an APS device. This present invention addresses these problems that exist within the prior art by simplifying the circuitry used in addressing the imager.
SUMMARY OF THE INVENTION
The present invention relates to the field of solid state photo-sensors and imagers, specifically imagers referred to as active pixel sensors (APS). It consists of a new method of row selection that eliminates the need for a separate row select transistor or gate per pixel, by eliminating the need for a separate row select buss in one case, and eliminating the need for a row select transistor in another case, while maintaining the ability to selectively address rows of the APS device. By employing a method of generating row select signals for active pixel sensors comprising the steps of: providing an active pixel sensor having a plurality of pixels arranged in columns and rows; and selecting rows within the active pixel sensor by application of a supply voltage to the supply of the in pixel amplifiers within a predetermined row to be selected and removal of the supply voltage from the supply of the in-pixel amplifiers of unselected rows.
A prior art APS pixel is shown in FIG.
1
. The pixel comprises a photodetector (PDET), that can be either a photodiode (PD) or photogate (PG), transfer gate (TG), floating diffusion (FD), reset transistor (RES), with a reset gate (RG), row select transistor (ROWST), with a row select gate (RSG), and signal transistor (SIG) which has its gate connected to floating diffusion and operates as an amplifier for the photocharge stored on the floating diffusion. Pixels are arranged in an array (X-columns and Y-rows), to form an image sensor. Incident light creates electrons in the photodetector. These electrons are transferred onto the floating diffusion which is connected to the gate of SIG. This signal is read out by selecting the desired row (turning on the desired ROWST) by application of an “on-voltage” to the gate of ROWST), and then selecting each column separately. All other rows are “turned-off” by applying the appropriate signal to the gate of ROWST for those rows. Hence when selecting a specific column (the details of this operation are not relevant to this invention), the signal present on that line will be determined by which row is selected (i.e. the row in which ROWST is turned on). A simplified schematic of a single column is provided in FIG.
2
. The output voltage V
0
, is determined by which row transistor is turned-on, since all other signal transistors are essentially disconnected.
This invention provides a means for reducing the components required for row selection. In the first architecture, the separate row select buss is eliminated. In the second architecture, row selection is accomplished without using a row select transistor per pixel. Two physical embodiments of the new pixel architectures are shown in
FIGS. 3A and 3B
. Other specific physical embodiments are realizable. These two are chosen for illustration.
In the first architecture (shown in
FIG. 3
a
), the pixel comprises a PD, TG, FD, RES, RG, SIG, ROWST and row select signal line (ROWSIG). It does not contain a separate row select gate or buss (RSG). In this architecture, row selection is accomplished by applying the supply voltage VDD to the desired ROWSIG while applying OV to the remaining ROWSIG's. The SIG transistor
35
which has its gate connected to floating diffusion
26
operates as an amplifier for the photocharge stored on the floating diffusion
26
. This effectively switches the supply side of the SIG
35
transistor amplifier from VDD to 0 volts. It will be understood by those skilled in the art that while the preferred embodiment of the present invention switches the supply side to the SIG
35
transistor amplifier by connecting ROWSIG to the drain of the SIG
35
transistor amplifier and applying differing potential substantially equal to VDD or 0 volts, that an equivalent result can be achieved by reversing the polarity. To reverse the polarity that switches the supply side of the SIG
35
transistor amplifier, the ROWSIG would then be connected to the source of the SIG
35
transistor amplifier and potentials voltages differing from essentially 0 volts to GROUND. A simplified schematic of one column is provided in FIG.
4
. The output voltage is determined by which ROWSIG that VDD is applied to, similar to prior art except that only one buss per row is used to accomplish row select, ROWSIG, rather than 2 busses, VDD and RSG. The area that was previously used for RSG can now be used for the PD, thus improving the fill factor and sensitivity of the pixel.
The pixel in
FIG. 3B
comprises a PD, TG, FD, RES, RG SIG and row select signal line (ROWSIG). It does not contain a separate row select transistor or buss (ROWST and RSG). In this architecture, row selection is accomplished by applying the supply voltage VDD to the desired ROWSIG while floating the remaining ROWSIG's. A simplified schematic of one column is provided in FIG.
5
. The output voltage is determined by which ROWSIG that VDD is applied to, similar to prior art except that only one row select switch per row is used rather than one per pixel. The area that was previously used for ROWST can be used for the PD, thus improving the fill factor and sensitivity of the pixel.
These and other aspects, objects, features and advantages of the present invention will be more clearly understood and appreciated from a review of the following detailed description of the preferred embodiments and appended claims, and by reference to the accompanying drawings.
ADVANTAGEOUS EFFECT OF THE INVENTION
The present invention provides an advantage in that it uses less semiconductor area for control circuitry allowing more area for photodetector, thereby improving the fill factor.


REFERENCES:
patent: 5144447 (1992-09-01), Akimoto et al.
patent: 5631704 (1997-05-01), Dickinson et al.
patent: 0 719 048 A2 (1996-06-01), None
Copy of European Search Report, dated May 31, 1999.

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