Active pixel sensor with enhanced reset

Television – Camera – system and detail – Solid-state image sensor

Reexamination Certificate

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Details

C348S230100

Reexamination Certificate

active

06784930

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to active pixel sensors and, more specifically, to rapid and complete reset of pixel cells within these sensors.
BACKGROUND OF THE INVENTION
Active pixel sensors (APSs) capture digital image data and are often used in digital still cameras, digital video cameras and image copying apparatus, etc. APSs are typically formed of a plurality of pixel cells that each contain a photo-sensitive diode, commonly referred to as a photo diode. Representative APS array sizes include 352 rows×288 columns (CIF) and 640 rows×480 columns (VGA). Array densities are expected to increase in the future.
Before an image is captured (i.e., before a picture is taken) with an APS, picture parameters for the proposed image are preferably sampled to obtain data for exposure and focus algorithms. These algorithms may achieve auto focusing, white balance, RGB voltage equalization, exposure time/gain boost adjustment, etc.
Initial picture parameter determination is typically achieved in a process called “sampling” in which the pixels are exposed to the incident light of a proposed image. The amount of time required to read and reset each pixel and calculate the difference between the exposed and reset voltage levels (representative of the intensity of incident light) is, however, disadvantageously long. To reduce this delay, a procedure termed “sub-sampling” has been developed.
In sub-sampling, a smaller portion of the array, or several small portions of the array are exposed during initial picture parameter determination, but not the entire array. A tradeoff is sought between exposing a sufficient number of pixels for accurate sensing and reducing the number of pixels sampled to increase processing time.
If the chosen sub-sampling technique, for example, selects alternate rows or groups of alternate rows, this trade off may be effectively achieved, but not without the introduction of some disadvantageous aspects. One of these disadvantageous aspects is that reset of a “portion” of the array, but not reset of the entire array, produces pixels that have different reset values (due to leakage current and additive reset effects, etc.). This results in an inaccurate APS output signal and the occurrence of these artifacts in the resultant image. This problem is exacerbated when the proposed image is dark. In this instance, only a small amount of photo diode discharge occurs, resulting in an increased reset value (due to additive effect) and greater differences between reset values of sampled and non-sampled pixel cells.
One possible manner of alleviating the problem of different reset values is generation of a global reset signal that would sequentially reset each of the pixel rows. Sequential reset is preferred because simultaneous or parallel reset would produce unacceptably high EMI due to the large number of simultaneous signal transitions. The generation of sequential reset or the like for the entire array, however is disadvantageously long.
Therefore, a need exists for an APS that permits sub-sampling but which allows rapid and accurate reset of substantially all pixels.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an APS that permits rapid sub-sampling and reset of substantially all of the pixel cells in the array.
It is another object of the present invention to provide an APS with look ahead (or behind) reset that resets portions of an array not read in a sub-sampling or like operation.
It is also an object of the present invention to provide such an APS that operates in a rapid, low-cost and low-EMI manner.
These and related objects of the present invention are achieved by use of an active pixel sensor with enhanced reset as described herein.
In one embodiment, the present invention includes combinational logic that is provided between sub-sampled rows and non-sub-sampled rows. This logic senses when the circuit is operating in sub-sampling mode and generates reset signals for the non-sampled rows when the sampled rows are reset. This arrangement provides a low-cost, rapid and efficiently implemented manner of providing universal reset following a sub-sampling event.
In another embodiment, reset of the sub-sampled and non-sub-sampled rows after a sub-sampling event may be implemented in the reset control logic at the control logic level.
The attainment of the foregoing and related advantages and features of the invention should be more readily apparent to those skilled in the art, after review of the following more detailed description of the invention taken together with the drawings.


REFERENCES:
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patent: 5828406 (1998-10-01), Parulski et al.
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patent: 6493030 (2002-12-01), Kozlowski et al.
patent: 6529236 (2003-03-01), Watanabe
patent: 6583416 (2003-06-01), Villani
patent: 2002/0101528 (2002-08-01), Lee et al.
patent: 2003/0193597 (2003-10-01), Fossum et al.

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