Active pixel sensor with capacitorless correlated double...

Details Active pixel sensor with capacitorless correlated double... Active pixel sensor with capacitorless correlated double...

1998-05-19

2003-03-18

Garber, Wendy R. (Department: 2712)

Television

Camera, system and detail

Combined image signal generator and general image signal...

C348S308000

Reexamination Certificate

active

06535247

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electronic imaging devices and, in particular, to low-noise MOS-based imagers having minimal analog components in each pixel. The invention provides both a method and apparatus for significantly improving cancellation of reset noise in an MOS active pixel sensor (APS).
2. Description of Related Art
The prior art describes many alternatives to CCD sensors for generating video or still images. The various schemes can be grouped into two basic classes, depending upon whether signal amplification is performed at each pixel or in support circuits. In the passive-pixel sensor, pixel simplicity and optical fill factor are maximized. Active-pixel sensors (APS's) include an amplifier at each pixel site to instead optimize signal transfer and sensitivity.
The simplest passive pixel comprises a photodiode and an access transistor wherein the photo-generated charge is passively trnsferred from each pixel to downistream circuits. The integrated charge must, however, be efficienfly transferred with low noise and low nonuniformity. Since each column of pixels often shares a common row or column bus for reading the signal, noise and nonuniformity suppression are typically facilitated in the “column” buffer servicing each bus. One prior approach shown in
FIG. 1
, and having capacitor
2
, transistors
4
,
14
, and
16
, pixel sensor
8
, and assembly
6
, used a buffer consisting of a transimpedance amplifier with capacitive feedback to yield reasonable sensitivity considering the large bus capacitance. Since such charge-amplification means were not generally practical for on-chip implementation in early MOS imaging sensors, alternative means compatible with NMOS technology were used. One approach which was mass-produced by Hitachi for camcorders is described in “MOS Area Sensor, etc . . . ” Parts I and II″ in IEEE Trans. Electron Devices, ED-27 (8), August, 1980, pp. 1676-1687. The key refinements with respect to the approach of
FIG. 1
include anti-blooming control and circuitry for reducing fixed pattern noise. Though these imagers were inferior to the emerging charge coupled device (CCD) imagers available at the time, similar MOS imagers are still being offered commercially.
Subsequent efforts at improving passive-pixel imager performance have also focused on column buffer enhancements. One improvement to the column buffer involved using an enhancement/depletion inverter amplifier to provide reasonably large amplification in a small amount of real estate; its 40 1ux (1x) sensitivity was nevertheless nearly an order of magnitude below that of competing CCD-based sensors. Another improvement both enhanced sensitivity and facilitated automatic gain control via charge amplification in the column buffer. Recently, those working in the art have revisited the original capacitive-feedback transimpedance amplifier (CTIA) concept of
FIG. 1
because the CTIA appears to the inventors to be nearly ideal for passive-pixel readout if issues with temporal noise pickup and fixed-pattern noise are adequately addressed.
Though much progress has been made in developing passive-pixel imagers, their temporal S/N performance is fundamentally inferior to competing CCD imagers because the bus capacitance translates to read noise of ≈100 e-. CCDs, on the other hand, typically have read noise of 20 to 40 e- at video frame rates. Nevertheless, the allure of producing imagers in conventional MOS fabrication technologies rather than esoteric CCD processes (which usually require many implantation steps and complex interface circuitry in the camera) has encouraged the development of active-pixel sensors that can better compete with CCDs.
It appears to the inventors that the first step in such development is to mitigate the noise associated with the bus capacitance. One approach has been to add amplification to the pixel via the phototransistor by means of a Base-Stored Image Sensor (BASIS) which uses a bipolar transistor in emitter follower configuration together with a downstream correlated double sampler to suppress random and temporal noise. By storing the photogenerated-signal on the phototransistor's base to provide charge amplification, the minimum scene illumination was reportedly reduced to 10
−3
1x) in a linear sensor array. However, the minimum scene illumination was higher (10
−2
1x) in a two-dimensional BASIS imager having 310,000 pixels because the photoresponse nonuniformity was relatively high (≦2%). These MOS imagers had adequate sensitivity, but their pixel pitch was too large at about 13 &mgr;m. It has thus appeared desirable to the inventors to shrink the pixel pitch while also reducing photoresponse nonuniformity.
Since the incorporation of bipolar phototransistors is not strictly compatible with mainstream CMOS processes, others have segregated photodetection and signal amplification in an active-pixel sensor essentially comprising a three-transistor pixel with photodiode. All such proposals still offer inadequate performance. One approach discussed in U.S. Pat. No. 5,296,696, for example, augments the basic source-follower configuration with a column buffer that cancels fixed pattern noise, but adds a fourth transistor that creates a floating node vulnerable to generation of random offsets from charge-pumping and concomitant charge redistribution. U.S. Pat. No. 5,043,820 offers a method for injecting charge to reduce offset errors, but not with adequate accuracy and resolution to be useful for competing with CCDs. Furthermore, these and other similar approaches which require 3-4 transistors in the pixel (at least one of which is relatively large to minimize amplifier 1/f noise) in addition to the photodiode, also require off-chip signal processing for best S/N performance because none addresses the dominant source of temporal noise, namely the reset or “KTC” noise.
In order to eliminate or greatly suppress the reset (kTC) noise generated by resetting the detector capacitance, a dedicated memory element is usually needed, either on-chip or off-chip, to store the reset voltage to apply correlated double sampling and coherently subtract the correlated reset noise while the photo-generated voltage is being read. U.S. Pat. No. 5,471,515 subsequently addressed this basic deficiency by developing an APS that uses intra-pixel charge transfer to store the reset charge at each pixel at the start of each imaging frame. This floating gate APS facilitates correlated double sampling with high efficiency by adding several transistors and relying on a photogate for signal detection.
As those skilled in the art will appreciate, in conventional correlated double sampling (CDS) the reset noise is sampled, stored and later subtracted from the composite signal level. Both temporal and spatial noise are reduced since the reset noise is correlated within each frame. CDS, however, requires a storage means for each pixel that resides either on- or off-chip. Adding the memory element to each pixel compromises the pixel optical fill factor or often requires circuit elements not strictly compatible with standard CMOS processes. One alternative—adding the memory cell to the integrated circuit—greatly adds to the chip area and associated fabrication cost. A second alternative—providing the memory in support electronics—requires both full frame memory to store the reset levels on a frame-by-frame basis and signal processing electronics to digitally subtract the stored reset values.
The drawbacks of various prior art approaches are intractable because they increase imager cost. For example, the '515 patent approach adds several transistors to each pixel and several million transistors to each imager thereby reducing production yield. The BASIS apparatus employing bipolar transistors is not compatible with standard CMOS gate fabrication so a nonstandard process must be developed. These deficiencies were subsequently addressed by Ackland U.S. Pat. Nos. 5,576,763 and 5,541,402; and by Chi in U.S. Pat. N

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