Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit
Reexamination Certificate
2000-02-14
2002-06-25
Allen, Stephone B (Department: 2878)
Radiant energy
Photocells; circuits and apparatus
Photocell controlled circuit
C348S308000
Reexamination Certificate
active
06410899
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to active pixel sensors. More particularly, the present invention relates to variable biasing of several of the transistors in an active pixel sensor to improve sensitivity, reduce noise, to provide compressive non-linearity in the charge-to-voltage gain, and to reduce leakage current in pixels during readout.
2. The Prior Art
In the art of CMOS active pixel sensors, the sensitivity, noise, and nature of the gain of an active pixel sensor present issues of concern. The sensitivity of an active pixel sensor in measuring the charge generated by the photons striking the active pixel sensor is typically characterized by determining the volts generated per photon of light striking the active pixel sensor and is termed charge-to-voltage gain. The readout amplifier in an active pixel sensor represents a substantial source of noise that in prior art pixel sensors has required design tradeoffs. The gain in prior art active pixel sensors is most often expansive, though it is preferred to be compressive.
The sensitivity of an active pixel sensor is determined by at least three factors. The first factor is related to the percentage of the area in the active pixel sensor available for converting photons to electrons. This is known as the fill factor. An increase in the area leads to an increase in the amount of charge generated. A second factor affecting the sensitivity of the active pixel sensor is related to the capacitance that is available for the integration of the charge sensed by the active pixel sensor. It will be appreciated that the voltage on the capacitor for given amount of charge is inversely proportional to the size of the capacitor. Accordingly, when the capacitance increases, the voltage decreases for the same amount of charge. A third factor is the gain of the readout amplifier for the active pixel sensor. Since the readout amplifier in the prior art is typically a transistor configured as a source follower, the gain is less than one.
One source of noise in an active pixel sensor is created by threshold fluctuations in the readout transistor. The amount of threshold fluctuation is related to the size of the readout transistor. As the size of the readout transistor is increased, the amount of threshold fluctuation, and hence the amount of noise decreases.
In compressive nonlinear gain, the gain at high light levels is less than the gain at low light levels. Those of ordinary skill in the art will appreciate that it is typically desirable to have greater sensitivity in converting photons-to-voltage at lower rather than higher light levels, because this increases the signal-to-noise ratio at lower light levels and, accordingly, the usable dynamic range of the active pixel sensor is increased.
The CMOS active pixel sensor art includes active pixel sensors that may or may not have embedded storage.
FIGS. 1 and 3
illustrate typical CMOS active pixel sensors without and with embedded storage, respectively.
In an active pixel sensor
10
of
FIG. 1
, a photodiode
12
employed to collect charge has an anode coupled to a fixed voltage potential, shown as ground, and a cathode coupled to the source of an MOS N-channel Reset transistor
14
and the gate of an MOS N-Channel Source-Follower transistor
16
. The gate of MOS N-channel Reset transistor
14
is coupled to a RESET line, and the drain of MOS N-channel Reset transistor
14
is coupled to a voltage reference, Vref. The drain of MOS N-channel Source-Follower transistor
16
is coupled to a fixed potential Vcc, and the drain of MOS N-channel Source-Follower transistor
16
is coupled to an MOS N-Channel Row-select transistor
18
. MOS N-Channel Row-select transistor
18
couples the active pixel sensor
10
to a row-select line
20
and a column output line
22
of an array of active pixel sensors. Typically, the voltage Vref and the voltage Vcc are the same. In the active pixel sensor
10
, the capacitance available for the integration of the charge sensed by the active pixel sensor
10
includes the photodiode
12
capacitance and the gate capacitance of the MOS N-Channel Source-Follower transistor
16
.
The operation of the active pixel sensor
10
as it is typically performed is well understood by those of ordinary skill in the art.
FIG. 2
is a timing diagram illustrating the operation of active pixel sensor
10
. The active pixel sensor
10
is first reset by a RESET signal, during a reset step, that turns on MOS N-Channel Reset transistor
14
to place the voltage Vref on the cathode of the photodiode
12
. An integration step begins when the RESET signal is de-asserted (makes a transition from HIGH to LOW) after which photo-generated electrons are collected on the cathode of the photodiode
12
and reduce its voltage from the value Vref placed there during the reset step. During a subsequent readout step, a ROW SELECT signal will be asserted on row-select line
20
to turn on MOS N-Channel Row-select transistor
18
to place the voltage at the source of MOS N-Channel Source-Follower transistor
16
on the column output line
22
for sensing. It should be appreciated that the voltage on the gate of MOS N-Channel Source-Follower transistor
16
formed by the charge accumulated on the cathode of the photodiode
12
will be followed by the source of MOS N-Channel Source-Follower transistor
16
during the readout period.
FIG. 3
is a schematic diagram of a CMOS active pixel sensor
30
having embedded storage. As in the active pixel sensor
10
of
FIG. 1
, the active pixel sensor
30
of
FIG. 3
includes a photodiode
12
having an anode that is coupled to ground and a cathode that is coupled to the source of MOS N-channel Reset transistor
14
. The gate of MOS N-channel Reset transistor is coupled to a RESET line, and the drain of MOS N-channel Reset transistor
14
is coupled to a voltage Vref. The cathode of photodiode
12
is also coupled to the gate of MOS N-channel Source-Follower transistor
16
. The drain of MOS N-channel Source-Follower transistor
16
is coupled to Vcc, and the source of MOS N-channel Source-Follower transistor
16
is coupled to MOS N-channel Row-select transistor
18
. Typically, the voltage Vref and the voltage Vcc are equal to one another. As in the active pixel sensor of
FIG. 1
, MOS N-Channel Row-select transistor
18
couples the active pixel sensor
10
to a row-select line
20
and a column output line
22
of an array of active pixel sensors. In the active pixel sensor
30
of
FIG. 3
, the cathode of photodiode
12
is coupled to the MOS N-Channel Source-Follower transistor
16
through MOS N-channel Transfer transistor
32
. The gate of MOS N-channel Transfer transistor
32
is coupled to a XFR line, and the drain of MOS N-channel Transfer transistor
32
is coupled to a first plate of a capacitor
34
and to the gate of MOS N-channel Source-Follower transistor
16
.
In the active pixel sensor
30
of
FIG. 3
, the capacitance available for the integration of the charge sensed by the active pixel sensor
30
includes the capacitance of the photodiode
12
, the capacitance of the storage capacitor
34
, and the gate capacitance of the MOS N-Channel Source-Follower transistor
16
. It should be appreciated, however, that because the voltage at the drain of the MOS N-Channel Source-Follower transistor
16
is high, the gate capacitance of the MOS N-Channel Source-Follower transistor
16
is small and is thus not typically a preferred charge storage element.
FIG. 4
is a timing diagram corresponding to the operation of active pixel sensor
30
. To operate the active pixel sensor
30
, the MOS N-channel transistor
14
is first turned on by a RESET signal to place the voltage Vref at the cathode of the photodiode
12
just as in the active pixel sensor of FIG.
1
. The MOS N-channel Transfer transistor
32
is also turned on by a XFR signal asserted on the XFR line at this time to place the voltage Vref on the storage capacitor
34
. MOS N-channel Reset transistor
14
is then turned off while MOS N-c
Dong Milton B.
Lyon Richard F.
Merrill Richard B.
Turner Richard M.
Allen Stephone B
Foveon, Inc.
Sierra Patent Group Ltd.
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