Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal – Responsive to electromagnetic radiation
Reexamination Certificate
2002-11-26
2004-11-30
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making device or circuit responsive to nonelectrical signal
Responsive to electromagnetic radiation
C438S057000, C438S059000, C438S066000, C438S048000, C438S073000, C438S075000
Reexamination Certificate
active
06825059
ABSTRACT:
ORIGIN OF THE INVENTION
The invention described herein was made in the performance of work under a NASA contract, and is subject to the provisions of Public Law 96-517 (35 USC 202) in which the Contractor has elected to retain title.
FIELD OF THE INVENTION
The invention is related to semiconductor imaging devices. More specifically, the present invention relates to a silicon imaging device which can be fabricated using a CMOS compatible process, and specific improved techniques that are used by such a system.
BACKGROUND AND SUMMARY
Many semiconductors can be used for acquiring a signal indicative of an image. Charge coupled devices (CCDs), photodiode arrays, charge injection devices and hybrid focal plane arrays are some of the more commonly used devices. CCDs are often used, since they represent a mature technology, are capable of large formats and very small pixel size and they facilitate noise-reduced charge domain processing techniques such as binning and time delay integration.
However, CCD imagers suffer from a number of drawbacks. For example, the signal fidelity of a CCD decreases as the charge transfer efficiency is raised to the power of the number of stages. Since CCDs use many stages, the CCD fabrication technique needs to be optimized for very efficient charge transfer efficiency. CCDs are also susceptible to radiation damage, require good light shielding to avoid smear and have high power dissipation for large arrays.
The specialized CCD semiconductor fabrication process is intended to maximize the charge transfer efficiency of the CCD. This specialized CCD process, however, has been incompatible with the complementary metal oxide semiconductor (“CMOS”) processing which has been conventionally used. The image signal processing electronics required for the imager are often fabricated in CMOS. Accordingly, it has been difficult to integrate on-chip signal processing electronics in a CCD imager, because of the incompatibility of the processing techniques. Because of this problem, the signal processing electronics has often been carried out off-chip.
Typically, each column of CCD pixels is transferred to a corresponding cell of a serial output register, whose output is amplified by a single on-chip amplifier (e.g., a source follower transistor) before being processed in off-chip signal processing electronics. This architecture limits the read-out frame rate which the on-chip amplifier can handle proportional to the number of charge packets divided by the number of pixels in the imager.
The other types of imager devices have problems as well. Photodiode arrays exhibit high kTC noise. The KTC noise makes it impractical to reset a diode or capacitor node to the same initial voltage at the beginning of each integration period. Photodiode arrays also suffer from lag. Charge injection devices also have high noise.
Hybrid focal plane arrays exhibit less noise but are prohibitively expensive for many applications and have relatively small array sizes.
In view of the inventors recognition of the above problems, it is one object of the present invention to provide an imager device which has the low kTC noise level of a CCD without the associated CMOS incompatibility and other above-described problems.
In addition, there is a need in imaging devices to control the integration or exposure time of the sensor. This control allows decreasing the integration time for imaging relatively bright objects to avoid saturating the pixels. Conversely, it is sometimes desirable to increase the integration time to increase the resolution of relatively dim objects.
Control of the integration time is also advantageous in video imaging applications where it is desired that this period be less than the inverse of the frame rate. Thus, if the integration period is T and the frame rate is f, it is desirable that T≦1/f.
Integration time has been controlled in the past with mechanical shutters. However, the mechanical nature of these devices made the shuttering imprecise. This caused the integration time to vary significantly. In addition, once configured, the mechanical-type shutters could not easily be adjusted, for example, to shutter a different portion of the array or to change adaptively. A controllable electronic shutter in each pixel cell would provide a more efficient, precise, and versatile way of setting the integration time of the array or a part of the array.
Furthermore, it is advantageous in some applications that some or all the pixels be integrated simultaneously for the same absolute period of time. This simultaneous integration prevents motion skew in the image by providing a “stop-action” or “snap shot” image. The alternative to simultaneous integration is to accumulate charge in only a portion of the pixel cells being employed to image an observed scene. For example, an imaging system might operate by scanning a row of the array at a time to produce an overall image. Thus, the resultant image has a series of lines, each of which represents a part of the observed scene at a different time. Obviously, if the scene is changing quickly enough, the image will be skewed as stated above. Therefore, this piecemeal method of creating an image would be inappropriate for certain quickly changing scenes. However, by integrating all the pixels in the array simultaneously and capturing the accumulated charge, a “snap shot” of the scene encompassing the period of integration can be obtained. The captured accumulated charge would then be readout and processed in some sequential method to create the desired image.
In view of the above, one aspect of the present invention is embodied in an imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process. The integrated circuit includes a focal plane array of pixel cells, each one of the cells including a photosensing element, e.g., a photogate, overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.
In a preferred embodiment, the sensing node of the charge coupled device section includes a floating element—e.g., a diffusion, and the charge coupled device stage includes a transfer gate overlying the substrate between the floating diffusion and the photogate. This preferred embodiment can further include apparatus for periodically resetting a potential of the sensing node to a predetermined potential, including a drain diffusion connected to a drain bias voltage and a reset gate between the floating diffusion and the drain diffusion, the reset gate connected to a reset control signal.
The imaging device also includes a readout circuit having at least an output transistor. Preferably, the output transistor is a field effect source follower output transistor formed in each one of the pixel cells, the floating diffusion being connected to its gate. Also, the readout circuit can further include a field effect load transistor connected to the source follower output transistor, and preferably a correlated double sampling circuit having an input node connected between the source follower output transistor and load transistor. The focal array of cells is also preferably organized by rows and columns, and the readout circuit has plural load transistors and plural correlated double sampling circuits. In this case, each cell in each column of cells is connected to a single common load transistor and a single common correlated double sampling circuit. These common load transistors and correlated double sampling circuits are disposed at the bottom of the respective columns of cells to which they are connected.
In the preferred implementation, charge is first accumulated under the photogate of a pixel cell. Next, the correlated double sampling circuit samples the floating
California Institute of Technology
Fish & Richardson P.C.
Pham Long
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