Active memory processing array topography and method

Details Active memory processing array topography and method Active memory processing array topography and method

2006-11-07

2006-11-07

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

Reexamination Certificate

active

07133998

ABSTRACT:
An integrated active memory device includes an array of processing elements coupled to a dynamic random access memory device and to a component supplying instructions to the processing elements. The processing elements are logically arranged in a plurality of logical rows and logical columns. The array is logically folded to minimize the length of the longest path between processing elements by physically interleaving the processing elements so that the processing elements in different logical rows a physically interleaved with each other and the processing elements in different logical columns a physically interleaved with each other.

REFERENCES:
patent: 4800383 (1989-01-01), Considine
patent: 5552722 (1996-09-01), Kean
patent: 5689661 (1997-11-01), Hayashi et al.
patent: 5737628 (1998-04-01), Birrittella et al.
patent: 6470441 (2002-10-01), Pechanek et al.
patent: 6598145 (2003-07-01), Dally et al.
patent: 6728862 (2004-04-01), Wilson
patent: 6769056 (2004-07-01), Barry et al.
patent: 0 444 368 (1991-09-01), None
patent: 2 276 743 (1994-10-01), None

Affiliated with

Also associated with

Rating

Active memory processing array topography and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Active memory processing array topography and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Active memory processing array topography and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3682088