Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
1998-11-05
2001-05-15
Abraham, Fetsum (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S072000, C257S347000, C257S348000, C257S349000, C257S350000, C257S351000, C257S352000, C257S353000, C349S139000, C349S142000
Reexamination Certificate
active
06232620
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to an active matrix type TFT elements array and, more particularly, to an active matrix type TFT elements array provided on an insulating substrate and which can be conveniently used for an active matrix type liquid crystal display.
BACKGROUND
There is an increasing demand for a liquid crystal display. In particular, the demand for an active matrix type liquid crystal display, in which thin film field-effect transistors are arrayed as switches for respective pixels on a glass substrate, is rapidly increasing because of its high picture quality.
FIG. 7
illustrates the structure of a conventional thin film field-effect transistor elements array used in an active matrix type liquid crystal display. Specifically,
FIG. 7
a
is a plan view,
FIG. 7
b
is a cross-sectional view taken along line A-A′ of
FIG. 7
a
and
FIG. 7
c
is a cross-sectional view taken along line B-B′ of
FIG. 7
b.
In FIGS.
7
(
a-c
) show a thin film field-effect transistor, in which a gate metal film
2
, a drain metal film
6
a
and indium tin oxide (ITO) films
8
a
,
8
b
operate as a control line, a signal line and pixel electrodes, respectively. The ITO film
8
a
is connected via a contact hole
9
to a drain metal film
6
b
. The thin film field-effect transistor is a thin film transistor of an inverted staggered structure having an amorphous silicon semiconductor film
4
a
and a n+ amorphous silicone film
5
.
The above-described conventional thin film field-effect transistor elements array has the following disadvantages:
FIGS. 8
a
to
8
d
are step by step cross-sectional views taken along line B-B′ of
FIG. 9
for illustrating a process in which residuals of a photoresist film are produced during patterning of the ITO film
8
, and
FIG. 9
is a plan view thereof.
Referring to
FIG. 8
a
, the gate metal film
2
is formed and patterned on the light-transmitting insulating substrate
1
, and subsequently a gate insulating film
3
is formed. Although not shown in
FIG. 8
, the drain metal film is subsequently formed and patterned, and an insulating film
7
then is formed.
Referring to
FIG. 8
b
, an ITO film
8
is formed, and subsequently a photoresist film
10
is formed.
Referring to
FIG. 8
c
, residuals
11
of the photoresist film are sometimes formed at the time of light exposure and development.
In this case, if the ITO film
8
is etched, the ITO film
8
is not etched, such that, if the photoresist film
10
is removed, the ITO film
8
a
and the ITO film
8
b
are not removed and remain connected, as shown in
FIG. 8
d.
According to the inventor's view, this is the state in which the pixel electrodes in the longitudinal direction remain connected, as shown in FIG.
9
. If an active matrix display is formed using this transistor elements array, there are produced flaws of two consecutive pixels, thus significantly lowering the production yield.
As a method for prohibiting shorting on occurrence of photoresist film residuals, there is proposed in e.g., JP Patent Kokai JP-A-62-1711442 (1987) an interconnection forming method for semiconductor elements in which protrusions are formed in the insulating film between contact holes to produce random light scattering in a resist overlying the edges of the protrusions to permit strong light exposure of the edges of the light-exposed portions of the resist, and thus eliminating resist residuals to prevent shorting between the lines.
FIG. 10
shows a corresponding cross-sectional view, in which an element
13
is formed on a semiconductor substrate
12
and an insulating film
14
is formed thereon. At a mid portion of the neighboring elements is formed a protrusion
15
in the insulating film for connecting lines
16
a
,
16
b
via contact holes to the elements
13
, respectively.
If, in this structure, photoresist film residuals are produced between the lines
16
a
,
16
b
during patterning the lines
16
a
,
16
b
, the photoresist film is hardly left on the protrusion in the insulating film such that the metal film of the lines is not left on the protrusion in the insulating film. Therefore, the lines
16
a
,
16
b
are separated from each other, thus prohibiting the lowering of the production yield due to shorting of the lines.
According to the inventor's view, however, in the method shown in
FIG. 10
, one lithographic step is added for providing the protrusion in the insulating film, thus increasing the number of production steps.
As another method for prohibiting shorting on occurrence of photoresist film residuals, there is proposed in JP Patent Kokai JP-A-7-234419 (1995) a thin film transistor substrate having a groove surrounding the pixel electrode, as shown in the cross-sectional view of FIG.
11
.
Referring to
FIG. 11
, an insulating film
18
is formed on the light-transmitting insulating substrate
17
. An ITO film is formed and patterned, after forming a groove
19
. During this patterning an ITO film
20
a
and an ITO film
20
b
are designed inherently to be separated from each other.
If photoresist film residuals are generated in the thin film transistor substrate, shown in
FIG. 11
, the ITO film
20
a
and the ITO film
20
b
are separated from each other at the portion of the groove
19
, as a result of which the production yield can be prevented from being lowered.
According to the inventor's view, however, in this structure, one lithographic step is added for providing the groove
19
, thus increasing the number of production steps.
As discussed above, the conventional technique has the following disadvantages:
The first disadvantage is that the production yield is lowered in the conventional technique explained with reference to
FIGS. 7
to
9
.
The reason is that, during patterning of the photoresist, film residuals are created an, the ITO film is not separated, thus producing flaws in two neighboring consecutive pixels.
The second disadvantage is that the number of production steps is increased in the conventional technique explained with reference to
FIGS. 10 and 11
.
The reason is that one lithographic step is added in the line forming method of
FIG. 10
for forming the protrusion, and for forming the groove in the thin film transistor substrate shown in FIG.
11
.
SUMMARY OF THE DISCLOSURE
In view of the above-mentioned disadvantages of the conventional technique, it is an object of the present invention to provide an active matrix type TFT elements array without increasing the number of process steps and without lowering the production yield.
For accomplishing the above object according to one aspect of the present invention, there is provided an active matrix TFT elements array having gate lines, drain lines, amorphous silicon thin film field-effect transistors and pixel electrodes on a light-transmitting insulating substrate, the drain lines being formed in an upper layer compared with the gate lines, the array characterized in that an amorphous silicon semiconductor film of the same layer as an amorphous silicon semiconductor film constituting the amorphous silicon thin film field-effect transistor is provided in the shape of an island of a length not longer than an interval between adjacent drain lines on the gate lines between pixel electrodes disposed adjacent each other along a lengthwise direction of the drain lines.
According to a second aspect, generally, there is provided an active matrix TFT elements array wherein a protrusion is formed, between pixel electrodes disposed neighboring to each other along the direction of the drain lines, so as to leave a pattern of an elongated semiconductor film.
According to a third aspect, there is provided an active matrix TFT elements array in which signal lines and control lines are arranged in a lattice configuration on an insulating substrate, a first signal electrode is connected to the signal lines at an intersection of the signal lines and control lines, thin film transistors having gate electrodes connected to the control lines and each having a semiconductor layer, a
Abraham Fetsum
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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