Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only
Reexamination Certificate
1997-07-28
2002-01-01
Parker, Kenneth (Department: 2871)
Liquid crystal cells, elements and systems
Particular structure
Having significant detail of cell structure only
C345S098000
Reexamination Certificate
active
06335778
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an active matrix type liquid crystal display device integrated with a driving circuit for displaying images according to inputted digital image signals, and more particularly to a liquid crystal display device that is little affected by non-uniform properties of elements and that is capable of reducing the power consumption and the cost by a large amount by digitally driving all circuits.
BACKGROUND OF THE INVENTION
An active matrix type liquid crystal display device will be taken as an example to illustrate a conventional liquid crystal display device.
As shown in
FIG. 24
, the liquid crystal display device is composed of a pixel array (ARY), a scanning signal line driving circuit (GD) and a data signal line driving circuit (SD).
The pixel array ARY includes a plurality of scanning signal lines (GL
1
, GL
2
. . . ; the signal lines will be inclusively denoted as GLs) and a plurality of data signal lines (SL
1
, SL
2
, . . . ; the signal lines will be inclusively denoted as SLs) which cross with each other. A pixel (PIX) is provided in each region enclosed by two adjacent scanning signal lines GLs and two adjacent data signal lines SLs to form a matrix as a whole.
The data signal line driving circuit (SD), which is synchronized with a timing signal such as a clock signal (CKS), samples an inputted image signal (DAT), amplifies the image signal DAT as necessary, and writes the image signal DAT into the data signal line SL. The scanning signal line driving circuit GD, which is synchronized with a timing signal such as a clock signal (CKG), sequentially selects one of the scanning signal lines GLs, writes into the pixel PIX an image signal (image data) that has been written into the data signal line SL, and lets the pixel PIX retain the image data written into the pixel PIX, by controlling opening and closing of a switching element in the pixel PIX.
As shown in
FIG. 25
, the pixel PIX includes a pixel transistor (SW), as a switching element, composed of a field effect transistor and a pixel capacity composed of a liquid crystal capacity (CL) and a supplementary capacity (CS) that is added if necessary.
The data signal line SL is connected to one of two electrodes of the pixel capacity via the drain and source of the pixel transistor SW. The gate of the pixel transistor SW is connected to the scanning signal line GL. The other electrode of the pixel capacity is connected to a common electrode line which is common to all the pixels. The voltage applied to the liquid crystal capacity CL modulates the transmittance or reflectance of the liquid crystal, thereby enabling the liquid crystal to act as a display.
Incidentally, as to the conventional active matrix type liquid crystal display device, an amorphous silicon thin film formed on a transparent substrate such as glass is used as a material of the substrate of the pixel transistor SW, and ICs are externally provided to function as the scanning signal line driving circuit GD and the data signal line driving circuit SD.
Meanwhile we have seen in recent years the development of a technique for forming a pixel array and driving circuit in a monolithic manner by using a polycrystal silicon thin film, in response to various needs, for example, to improve the driving capabilities of pixel transistors for the realization of a big display screen, to cut down on the mounting costs of driving ICs, and to improve reliability in mounting. In pursuit of the realization of an even larger display screen and even lower costs, attempts are being made to form a transistor from a polycrystal silicon thin film on a glass substrate at a processing temperature below the distortion point (about 600° C.) of glass.
Such a liquid crystal display device integrated with a driving circuit has a configuration including, for example, a scanning signal line driving circuit (GD), a data signal line driving circuit (SD) and an pixel array (ARY) composed of pixels (PIXes) arranged in a matrix form, the circuits and pixels being provided on an insulating substrate (SUB), as shown in FIG.
26
. The scanning signal line driving circuit GD and the data signal line driving circuit SD are connected to a control circuit (CTL) and a voltage generating circuit (VGEN).
A method for writing image data into a data signal line will be explained next. There are two methods for driving a data signal line: analogue and digital. When an IC is externally provided, the external IC incorporates an amplifier circuit to secure a driving capability in either of the methods. However, the liquid crystal display device integrated with a driving circuit employs as composing elements polycrystal silicon thin film transistors, whose properties are non-uniform. If an analogue circuit such as an amplifier circuit is used, the non-uniform properties result in non-uniformity in the output voltage, which in turn causes vertical stripes to appear on the displayed image. Therefore, generally, a driving circuit with no internally provided amplifier circuit is employed in the liquid crystal display device integrated with a driving circuit.
The following will explain a point-to-point successive driving method, which is most typically used in the liquid crystal display device integrated with a driving circuit, as an example of the analogue method.
The point-to-point successive driving method includes a data signal line driving circuit composed of a scanning circuit (shift register; SR), a buffer circuit (BUF), and sampling circuits (SMPs) corresponding to respective colors of red (R), green (G) and blue (B), as shown in FIG.
27
. An image signal (DAT) inputted into an image signal line is written into a data signal line (SL) by opening and closing the sampling circuits SMPs in synchronization with an output pulse of each stage of the scanning circuit SR. The buffer circuit BUF latches in and amplifies an output signal out of the scanning circuit SR, and generates an inverse signal as necessary.
The method has an advantage of a very simple circuit arrangement, but has several disadvantages as well: Since the image signal DAT needs to be written into the data signal line SL in a short period of time (one dot period or approximately several times the dot period), the output impedance of an external circuit for supplying the image signal DAT should be low. Also, if the source of the image signal DAT is a digital signal, the image signal DAT needs to be converted to an analogue signal. Therefore, the total power consumption of the liquid crystal display device, including the power consumption at an external image signal generating section, becomes very large.
FIG. 28
shows a configuration example of the system. Since the image signal DAT is inputted to the data signal line driving circuit SD, the configuration needs a digital/analogue converter (DAC) and a buffer amplifier (AMP), consuming a very large amount of power.
Various configurations are possible for the data signal line driving circuit of a digital method. Here will be explained a multiplexer method for selecting one of externally supplied gray scale voltages and supplying the selected gray scale voltage to a data signal line directly (without amplifying). The following example illustrates a case in which the input image signal is of three bits (eight gray scales) with respect to each color of R, G, and B.
The data signal line driving circuit includes, as shown in
FIG. 29
, a scanning circuit (shift register; SR), nine (=3 bits×RGB) latch-in circuits (LATs), as many transfer circuits (TRFs) as the latch-in circuits LATs, three decoder circuits (DECs) respectively composed of eight (=2
3
) AND circuits, and twenty-four (=2
3
×RGB) analogue switches (ASWs).
To this data signal line driving circuit are supplied a clock signal (CKS), a start signal (SPS), a transfer signal (TRP), nine (=3 bits×RGB) digital image signals (SIGs), and eight (=2
3
) gray scale power supplies (VGSes). The data signal line driving circuit latches in the digital ima
Kubota Yasushi
Sakai Tamotsu
Shiraki Ichiro
Parker Kenneth
Sharp Kabushiki Kaisha
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