Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-06-02
2003-01-07
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S100000, C345S094000
Reexamination Certificate
active
06504522
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an active-matrix-type image display device including a plurality pixels arranged in a matrix form, a plurality of data signal lines arranged to correspond to the columns of the pixels, and a plurality of scanning signal lines arranged to correspond to the rows of the pixels, for displaying an image by supplying picture signals from the data signal lines in synchronization with scanning signals supplied from the scanning signal lines. More particularly, the present invention relates to an active-matrix-type image display device capable of providing a gray-scale display using a gray-scale voltage.
BACKGROUND OF THE INVENTION
A conventional active-matrix liquid crystal display device is a known example of the active-matrix-type image display device. As illustrated in
FIG. 15
, the conventional active-matrix liquid crystal display device includes a plurality of source lines SL, gate lines GL, a source driver
52
connected to the source lines SL, and a gate driver
53
connected to the gate lines GL. A pixel
60
is provided in each region enclosed by adjacent source lines SL and adjacent gate lines GL. The pixels
60
form a pixel array
51
in the form of a matrix.
The source driver
52
samples a picture signal DAT input in synchronization with timing signals such as a clock signal CKS and a start signal SPS, and applies the picture signal DAT to the source lines SL, after amplifying it if necessary. The gate driver
53
sequentially selects a gate line GL in synchronization with timing signals such as a clock signal CKG and a start signal SPG. When the switching elements in the pixels
60
connected to the selected gate line GL are turned ON, the picture signal DAT applied to the source lines SL is supplied to the pixels
60
. Each pixel
60
has an electrostatic capacity, and stores the picture signal DAT supplied.
By the way, in the conventional active-matrix liquid crystal display device, in general, the source driver
52
and gate driver
53
are provided as an external IC. By contrast, in order to reduce the packaging cost and improve the packaging reliability, as shown in
FIG. 16
, for example, a technique for producing a monolithic structure by forming the pixel array
51
and driving circuits, such as the source driver
52
and gate driver
53
, on a single insulating substrate
57
was reported recently. A power supply circuit
55
, and a control circuit
54
for supplying various control signals are connected to the driving circuits.
The following description will explain an example of the structure of the source driver
52
for displaying an image corresponding to input digital picture signals, in the conventional active-matrix liquid crystal display device. In this example, a multiplexer-type structure is adopted. According to the multiplexer-type structure, more than one kind of gray-scale voltages supplied from external devices are selected, and applied to the source lines without amplifying the voltages by an amplifier or the like. In order to simplify the explanation, it is assumed that the digital picture signals to be input are 3 bits (8 gray scales).
As illustrated in
FIG. 17
, the conventional source driver
52
includes one scanning circuit
61
and three latch circuits
62
a
,
62
b
,
62
c
, three transfer circuits
65
a
,
65
b
,
65
c
, one decoder circuit
63
, and eight analog switches
64
a
through
64
h
, with respect to a single stage, i.e., a single source line SL. Supplied to each stage are 3-bit digital picture signals DAT
1
through DAT
3
, a transfer signal TRP, and eight kinds of gray-scale voltages V
1
through V
8
as well as the clock signal CKS and start signal SPS. For example, the scanning circuit
61
, the latch circuits
62
a
,
62
b
,
62
c
, and the decoder circuit
63
are formed by a shift register, half-bit latch circuits, and eight AND circuits, respectively.
Referring now to
FIG. 18
, the following description will explain the operation of the source driver
52
. Here, in order to simplify the explanation, let's look at only the three source lines, SL
1
through SL
3
. GL
1
and GL
2
in
FIG. 18
are the waveforms of the scanning signals supplied from the gate driver
53
to the gate lines GL
1
and GL
2
, respectively.
In a horizontal period T
1
, the source driver
52
fetches the digital picture signals DAT
1
through DAT
3
when the latch circuits
62
a
,
62
b
,
62
c
are opened and closed in synchronization with an output Q of the scanning circuit
61
. In a horizontal flyback period subsequent to the horizontal period T
1
, the transfer signal TRP becomes active, and the digital picture signals DAT
1
through DAT
3
fetched in the horizontal period T
1
are transferred at a time to the decoder circuit
63
from the transfer circuits
65
a
,
65
b
,
65
c
. The digital picture signals DAT
1
through DAT
3
transferred to the decoder circuit
63
at a time are decoded into 8-bit signals in the decoder circuit
63
, and supplied to analog switches
64
a
through
64
h
, respectively. Then, one of the gray-scale voltages V
1
through V
8
is selected, and output to the source lines SL in a horizontal period T
2
. Thus, the digital picture signals corresponding to a single horizontal scanning period fetched in the scanning period T
1
are output at a time in the next horizontal period T
2
by the source driver
52
.
However, the above-mentioned conventional structure suffers from the following drawbacks. Namely, in this structure, since a single gray-scale voltage needs to be output to all of the source lines SL at a time, the peak of a current flowing in a gray-scale voltage line (the line to the source driver
52
from a gray-scale power supply for generating the gray-scale voltage) in the period shown by t
trf
in
FIG. 18
is several tens milliampere. In other words, since the gray-scale power supply is required to produce a driving force satisfying such a condition, the overall power consumption of the liquid crystal display device becomes inevitably very high. Moreover, the component parts of the gray-scale power supply are required to have a high withstanding voltage, resulting in an increase in the production cost.
In resent years, portable information terminals are in widespread use. In such a situation, the demand for a liquid crystal display as a display device of the portable information terminals are increasing because of the thinness of the liquid crystal display device. Since most of the portable information terminals are driven by butteries, the display devices for use in such terminals are strongly required to consume low power.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a low-power-consuming active-matrix-type image display device by reducing, particularly, the power consumption of a gray-scale power supply.
In order to achieve the above object, an active-matrix-type image display device for inputting a digital picture signal, according to the present invention, includes:
a plurality of pixels arranged in a matrix form;
a plurality of data signal lines arranged to correspond to the columns of the pixels;
a plurality of scanning signal lines arranged to correspond to the rows of the pixels;
gray-scale voltage generating means for generating gray-scale voltages of different levels;
a scanning signal line driving circuit for outputting a scanning voltage to the scanning signal lines; and
a data signal line driving circuit for selecting a gray-scale voltage according to the picture signal and outputting the gray-scale voltage to the data signal line, and is characterized by that the data signal line driving circuit has one scanning circuit for each data signal line, and selectively outputs the gray-scale voltage to the data signal lines in synchronization with sequential outputs of active signals from the scanning circuits in one horizontal period.
With this structure, the gray-scale voltage generating means generates gray-scale voltages of different levels corresponding to the number of gray scales of the dig
Kubota Yasushi
Sakai Tamotsu
Shiraki Ichiro
Edwards & Angell LLP
Hjerpe Richard
Neuner George W.
Nguyen Kevin M.
Sharp Kabushiki Kaisha
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