Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-06-17
2003-01-14
Saras, Steven (Department: 2775)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S099000
Reexamination Certificate
active
06507332
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an active-matrix-type image display having a plurality of video signal lines installed therein and its driving method.
BACKGROUND OF THE INVENTION
In an active-matrix-type liquid crystal display having an integrated driving circuit, it is necessary to provide driving circuits, such as a source driver and a gate driver on an insulating substrate made of glass, crystal, etc., as integral parts with a display section, and the driving circuits are normally formed by polysilicon thin-film MOS transistors (hereinafter, referred to as polysilicon TFTs).
However, the driving circuit using polysilicon TFTs has the disadvantage of a very slow operation speed as compared with a driving circuit using monocrystal silicon. In particular, in the case where a large-screen, high-capacity displaying operation is carried out in the source driver for driving the source bus line in the display section, since sift registers constituting the source driver fail to provide a sufficient operation speed, various methods for carrying out a driving operation without exceeding the speed of the shift registers constituted by polysilicon TFTs have been considered.
FIG. 18
shows an active-matrix-type liquid crystal display of a driving-circuit-build-in type using two systems of shift registers, which is one example of a method for decreasing the operation speed required for the sift registers. Referring to
FIG. 18
, an explanation will be given of a construction of a conventional active-matrix-type liquid crystal display of the driving-circuit-built-in type.
As illustrated in the Figure, in this liquid crystal display, source bus lines s
1
through s
N
and gate bus lines g
1
through g
M
are wired in warp and woof on an insulating substrate
101
so that a display section
102
is formed. On the substrate
101
on which the display section
102
is formed, a source driver
103
for driving the source bus lines s
1
through s
N
is formed at one end of the source bus lines s
1
through s
N
and a gate driver
104
for driving the gate bus lines g
1
through g
M
is formed at one end of the gate bus lines g
1
through g
M
.
In the display section
102
, each of portions, surrounded by the source bus lines s
n
(1≦n≦N) and the gate bus lines g
m
(1≦m≦M), forms a pixel
120
which is one unit of display. Referring to
FIG. 2
that is an explanatory drawing of one Embodiment of the present invention, an explanation will be given of the pixel
120
. The pixel
120
is constituted by a thin-film transistor
20
a
functioning as a switching element that is formed at an intersecting point between each source bus line S
n
and each gate bus line G
m
, a pixel electrode
20
b
to which video signal electric potentials D
1
, D
2
, etc. provided from the source bus lines S
n
are applied so as to drive a liquid crystal capacitor and a charge-holding capacitor
20
c
installed in parallel with the pixel electrode
20
b.
As illustrated in
FIG. 18
, the source driver
103
is constituted by two video signal lines
131
a
and
131
b
for inputting video signals VideoI and VideoII to the source bus lines s
1
through s
N
, a sampling circuit constituted by an analog switch
132
formed between the video signal lines
131
a
·
131
b
and the respective source bus lines s
1
through s
N
, and two systems of shift registers SRa and SRb for controlling the operation of the analog switch
132
.
The odd numbered source bus lines s
1
through s
N−1
are connected to the video signal line
131
a
so that the video signal VideoI is applied thereto. The even numbered source bus lines s
2
through s
N
are connected to the video signal lines
131
b
so that the video signal VideoII is applied thereto. The analog switch
132
is used for sampling the video signals VideoI and VideoII from the video signal lines
131
a
and
131
b.
The two systems of shift registers SRa and SRb are alternately connected to the source bus lines s
1
through s
N
so that the shift register SRa controls the operation (opening and shutting) of the analog switch
132
corresponding to the odd numbered source bus lines s
1
through s
n−1
, while the shift register SRb controls the operation of the analog switch
132
corresponding to the even numbered source bus lines s
2
through s
N
.
The respective parts constituting the source driver
103
are formed on the same substrate
101
by using polysilicon thin-films, etc.
FIG. 19
shows a timing chart upon driving the source driver
103
shown in FIG.
18
. Referring to
FIGS. 18 and 19
, an explanation will be given of the driving operation of the source driver
103
.
The activation of the two systems of shift registers SRa and SRb is controlled by a shift start signal SP shown in FIG.
19
. The shift register SRa is controlled by shift clock signals &phgr;A·/&phgr;A and the shift register SRb is controlled by shift clock signals &phgr;B·/&phgr;B. Signals whose phases are shifted from each other by a ¼ period (a sampling period t
0
corresponding to a value obtained by dividing the effective horizontal scanning period by the number of the effective source bus lines) are used as the shift clock signal &phgr;A and the shift clock signal &phgr;B. Accordingly, these shift clock signals &phgr;A·/&phgr;A·&phgr;B·/&phgr;B allow the two shift registers SRa and SRb to output waveforms whose phases are respectively shifted from each other by the sampling period t
0
to the analog switch
132
successively.
The video signals VideoI and VideoII, which are formed by outputting for the period
2
t
0
video signal electric potentials D
1
, D
2
, . . . , etc. that have been obtained by sampling an original video signal Video with its phase respectively shifted by period t
0
, are inputted to the two video signal lines
131
a
and
131
b
respectively. The method for forming the video signals VideoI and VideoII will be described later in detail.
In this case, the two analog switches
132
, each of which is controlled by one output of each of the registers SRa and SRb, are connected to the respectively different video signal lines
131
a
and
131
b
, and successively sample the video signal electric potentials D
1
, D
2
, . . . , etc. having mutually different phases, as in the cases of video signals VideoI and VideoII shown in FIG.
19
. The analog switch
132
is allowed to conduct during a period in which the output of each of the shift registers SRa and SRb goes high, and one output of each of the shift registers SRa and SRb allows one of the analog switches
132
to conduct for period
4
t
0
.
During the period in which the analog switch
132
is allowed to conduct, the video signal VideoI or VideoII is sampled so that the source bus lines s
1
through s
N
are successively driven. Since the analog switch
132
in question is connected to the same video signal lines
131
a
and
131
b
that are connected to the analog switch
132
connected to the source bus lines s
1
through s
N
located two lines before, it is allowed to conduct with an overlapping period of
2
t
0
with the analog switch
132
connected to the source bus lines s
1
through s
N
located two lines before. As a result, the video signals VideoI and VideoII are sampled during the last period
2
t
0
(the period in which no overlapping is made with the source bus lines s
1
through s
N
located two lines before).
By carrying out the driving operation as described above, the video signal electric potentials D
1
, D
2
. . . , etc., which are mutually shifted by the sampling period t
0
, are applied to the source bus lines s
1
through s
N
.
Here,
FIG. 20
shows one example of a video-signal forming circuit for converting an original video signal Video into two kinds of video signals VideoI and VideoII. Referring to
FIG. 20
, an explanation will be given of the construction of the video-signal forming circuit.
As illustrated in the Figure, an A/D conversion circuit, to which an original video signal Video is inputted and which. A/D converts the inputted original video
Jinda Akihito
Kuwabara Nobuhiro
Yoneda Hiroshi
Anyaso Uchendu O.
Conlin David G.
Penny, V John J.
Saras Steven
Sharp Kabushiki Kaisha
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