Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
2000-03-17
2004-04-20
Nguyen, Dung (Department: 2821)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
C349S038000
Reexamination Certificate
active
06724443
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display (LCD), and more particularly to an active matrix type display device employing a thin film transistor (TFT) with a structure conducive to size reduction of the display device.
2. Description of the Related Art
An LCD is a display device configured by sandwiching liquid crystal between opposing first and second substrates. Typically, arranged on the first substrate are TFTs serving as switching elements and pixel electrodes formed for each pixel. A counter electrode is disposed on the second substrate.
FIG. 1
is a plan view showing a first substrate of a conventional active matrix type LCD. A plurality of data lines
51
extend parallel to one another in the column direction, while a plurality of parallel gate lines
52
extending in the row direction intersect the data lines
51
. A TFT
53
and a pixel electrode
54
are provided corresponding to each intersection of a data signal (drain signal) line
51
and a gate signal line
52
.
FIG. 1
illustrates a delta arrangement in which adjacent rows are arranged shifted from one another in the row direction.
Each TFT
53
includes a semiconductor film
62
connected to a data signal line
51
via a contact
61
. This semiconductor film
62
further connects to a pixel electrode
54
via another contact
63
. The semiconductor film
62
intersects a gate line
52
in two locations, forming gates
64
,
65
, respectively.
When a predetermined voltage is applied to the gate signal line
52
, a channel is formed at the gates
64
,
65
of the semiconductor film
62
of the TFT
53
, turning on the TFT. The data voltage applied to the data signal line
51
is then applied to the pixel electrode
54
. The electric field thus generated drives the liquid crystal to indicate display according to the data voltage.
In the present specification, a TFT structure including two gates as described above is referred to as a double gate. When a double gate is adopted in the TFT
53
, TFTs having high resistances are connected in series. With this arrangement, it is possible to reduce undesired current that inadvertently leaks and flows when the TFTs are turned off, namely, the off-leak current.
Each semiconductor film
62
includes a capacitor region
62
a
overlapping the pixel electrode
54
. Overlapping a large region of the capacitor regions
62
a
located over the pixel electrode
54
, a storage capacitor electrode
55
extends along the row direction. The storage capacitor electrode
55
is formed in the same layer as the gate signal line
52
. Together with the capacitor regions
62
a
of each semiconductor region
62
a
, the storage capacitor electrode
55
forms a storage capacitor for retaining a voltage applied to each pixel electrode
54
.
On the second substrate opposing the first substrate having the above-described structure, components such as a counter electrode and a black matrix are formed. The counter electrode is formed on the entire surface so as to oppose the plurality of pixel electrodes. The black matrix is a light-shielding film formed in regions opposing the data lines
51
and the TFTs
53
to prevent light leakage from regions between the data signal lines
51
and the pixel electrodes
54
, or to prevent flow of leak current generated when light irradiates on the TFTs
53
. The black matrix is formed to be approximately 6 &mgr;m wider than the data signal lines
51
so that light leakage is prevented even when a slight alignment error exists between the two substrates. To simplify the drawing of
FIG. 1
, the actual black matrix is not drawn, but its width is indicated by BM.
The cross-sectional view along line A-A′ of
FIG. 1
is shown in FIG.
2
. The storage capacitor electrode
55
is arranged on a glass substrate
71
. The semiconductor film
62
of the TFT
53
is disposed on the storage capacitor electrode
55
, with a first gate insulating film
72
formed between the semiconductor film
62
and the storage capacitor electrode
55
. After providing an interlayer insulating film
73
on the semiconductor film
62
, a data line
51
is arranged. A planarizing film
74
and the pixel electrode
54
are sequentially formed. An orientation film
75
is then formed covering a plurality of pixel electrodes
54
. Provided further on top are liquid crystal and a counter substrate, neither of which is shown. The data signal line
51
and the pixel electrode
54
are spaced apart by a predetermined distance d so as to minimize parasitic capacitance. The distance d may be, for example, approximately 1 &mgr;m. The black matrix is formed spanning between the pixel electrode
54
and an adjacent pixel electrode
54
in order to prevent light leakage from the gap between d.
In recent years, it has been common to find active matrix type display devices employed as displays on portable electronic instruments, such as the view finders of digital still and digital video cameras. When mounting active matrix type display devices on portable instruments, there exist a need to accomplish size reduction of such devices in which the display screen size is reduced while maintaining the number of pixels.
The capacitance of the storage capacitor is proportional to the area in which the storage capacitor electrode
55
and the semiconductor film
62
overlap. In reducing the display screen size while maintaining the number of pixels, if size reduction is performed according to simple similitude, the capacitance of the storage capacitor becomes insufficiently small along with the reduction. It would therefore be impossible to appropriately retain the voltage applied to the pixel electrode
54
.
If the pixel size is reduced to maintain sufficient capacitance of the storage capacitor, the ratio of the area of the storage capacitor electrode
55
within one pixel proportionally increases. The region in which the storage capacitor electrode
55
is formed does not allow light transmission, as the storage capacitor electrode
55
providing the storage capacitance is composed of a metal film such as of chromium. Accordingly, decrease in the aperture ratio in pixels cannot be avoided when maintaining a fixed area of storage capacitor when the pixel size is reduced.
SUMMARY OF THE INVENTION
The purpose of the present invention is to provide a display device having a high aperture ratio while maintaining sufficient area for storage capacitance. Another purpose is to obtain a display device which suppresses coupling between the data lines and the semiconductor films constituting the capacitor electrodes.
According to the present invention, a storage capacitor is provided along a data line. Sufficient storage capacitance can thereby be provided while maintaining high aperture ratio. Using an electrode (a second storage capacitor electrode) for creating a storage capacitor, light can be shielded in a region between the data line and a pixel electrode while forming a storage capacitor. Further, by widening the data line to form a light-shielding portion, light leakage from a region between an end of the storage capacitor electrode and a gate signal line can be prevented.
Coupling between the data line and the first storage capacitor electrode can be suppressed by positioning the first storage capacitor electrode so as to avoid overlapping the data line. Further, coupling between the data line and the first storage capacitor electrode can also be minimized by providing a shielding film between the data line and the first storage capacitor electrode when forming the storage capacitor under the data line.
Formation of the first storage capacitor electrode can be facilitated by extending the semiconductor film that constitute the active layer of a transistor, and using the extended portion as the first storage capacitor electrode.
REFERENCES:
patent: 5608556 (1997-03-01), Koma
patent: 5666179 (1997-09-01), Koma
patent: 5710611 (1998-01-01), Suzuki et al.
patent: 5907380 (1999-05-01), Lien
patent: 5986723 (1999-11-01), Nakamura et al.
p
Matsuda Hiroshi
Nakatani Norio
Sano Keiichi
Yokoyama Ryoichi
Hogan & Hartson LLP
Nguyen Dung
Sanyo Electric Co,. Ltd.
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