Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2007-10-23
2007-10-23
Shalwala, Bipin (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000, C345S100000, C345S208000, C315S169300
Reexamination Certificate
active
10846550
ABSTRACT:
Buffer circuits are provided between outputs of a scanning line driver circuit and scanning lines. The buffer circuits each are configured to make rise or fall time of scanning signals at output sides of the buffer circuits substantially the same as or longer than those of the scanning signals at end terminals of the scanning lines when the scanning signals supplied to the scanning lines are rectangular in waveform.
REFERENCES:
patent: 6448954 (2002-09-01), Katoh et al.
patent: 2002/0154089 (2002-10-01), Yamazaki et al.
patent: 2003/0164685 (2003-09-01), Inukai
patent: 2003/0197673 (2003-10-01), Nakamura
Kovalick Vincent E.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Shalwala Bipin
Toshiba Matsushita Display Technology Co., Ltd.
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