Active matrix substrate having column spacers integral with...

Details Active matrix substrate having column spacers integral with... Active matrix substrate having column spacers integral with...

2000-09-27

2003-06-10

Ton, Toan (Department: 2871)

Liquid crystal cells, elements and systems

Particular structure

Having significant detail of cell structure only

C349S044000, C349S138000

Reexamination Certificate

active

06577374

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to an active matrix liquid crystal display panel and, more particularly, to an active matrix substrate incorporated in the active matrix liquid crystal display panel and a process for fabrication thereof.
DESCRIPTION OF THE RELATED ART
A typical example of the active matrix substrate is illustrated in
FIGS. 1 and 2
. In order to clearly show the layout of electrodes, insulating layers are removed from FIG.
1
. The prior art active matrix substrate includes a transparent insulating plate
41
. Conductive strips
42
b
are patterned on the major surface of the transparent insulating plate
41
at intervals, and extend in parallel in a direction of row. The conductive strips
42
b
serve as gate lines, and gate electrodes
42
a
project from the gate lines
42
b.
The gate electrodes
42
a
and the conductive strips
42
b
are covered with a gate insulating layer
43
.
Although plural semiconductor layers
44
are formed on the gate insulating layer
43
, only one semiconductor layer
44
is shown in
FIG. 1
, and the gate electrode
43
is overlapped with the semiconductor layer
44
. The semiconductor layer
44
has a rectangular shape, and provides a channel region.
Conductive strips
46
are formed on the gate insulating layer
43
at intervals, and extend in parallel in a direction of column. The gate electrodes
42
a
and, accordingly, the semiconductor layers
44
are located between the adjacent two conductive strips
46
. The conductive strips
46
serve as source lines, and source electrodes
46
a
project from the source lines
46
. The source electrode
46
a
is held in contact with one end portion of the semiconductor layer
44
through an ohmic contact layer
45
.
Although plural conductive layers are formed in regions each defined by the adjacent two source lines
46
b
and the adjacent two gate lines
42
b,
only one conductive layer
47
is shown in FIG.
1
. The conductive layer
47
serves as a drain electrode, and is held in contact with the other end portion of the semiconductor layer
44
through an ohmic contact layer
45
.
The gate electrode
42
a,
the gate insulating layer
43
, the semiconductor layer
44
, the source electrode
46
a
and the drain electrode
47
as a whole constitute a thin film filed effect transistor, and the thin film field effect transistor is covered with a passivation layer
48
. A pixel electrode
49
is formed on the passivation layer
48
, and the adjacent two source lines
46
b
and the adjacent two gate lines
42
b
are partially overlapped with the periphery of the pixel electrode
49
. The pixel electrode
49
is formed of transparent conductive material. A contact hole
51
is formed in the passivation layer
48
, and the pixel electrode
49
is held in contact with the drain electrode
47
through the contact hole
51
. The source line
46
b
is electrically connected through the thin film field effect transistor to the pixel electrode
49
.
The gate lines
42
b
are connected through contact holes formed in the gate insulating layer
43
to gate terminals
42
c
as shown in
FIG. 3
, and the source lines
46
b
are connected through contact holes formed in the passivation layer
48
to data terminals
46
c
as shown in FIG.
4
. Driving signals are selectively applied to the gate terminals
42
c,
and video data signals are selectively applied to the data terminals
46
c.
The thin film field effect transistor and the pixel electrode form a pixel together with a common electrode (not shown) and a piece of liquid crystal (now shown) between the pixel electrode
49
and the common electrode. The pixels are arranged in rows and columns, and are selectively energized for producing a picture on the active matrix liquid crystal display panel.
The driving signals are selectively propagated through the gate lines
42
b
to the gate electrodes
42
a,
and the associated thin film field effect transistors turn on so as to create conductive channels in the semiconductor layers
44
. The video data signals are selectively supplied through the source lines to the source electrodes
46
a,
and reach the pixel electrodes
49
through the conductive channels. Thus, the electric charge is selectively accumulated in the pixel electrodes, and the charged pixel electrodes make the associated pieces of liquid crystal transparent. As a result, an image is produced on the matrix of pixels.
The prior art active matrix substrate is fabricated through a process described hereinbelow with reference to
FIGS. 5A
to
5
K. The description is focused on the thin film field effect transistor, and the structure therearound.
The prior art process starts with preparation of the transparent insulting plate
41
. Conductive metal such as Al, Mo or Cr is deposited to 100 nanometers to 400 nanometers thick over the major surface of the transparent insulating plate
41
by using sputtering. Photo-resist solution is spread over the entire surface of the conductive metal layer, and is baked. A pattern image of the gate lines/gate electrodes/gate terminals is transferred from a photo-mask to the photo-resist layer, and a latent image is produced in the photo-resist layer. The latent image is developed so as to form a photo-resist etching mask on the conductive metal layer. Thus, the photo-resist etching mask is formed through photo-lithographic techniques. Using the photo-resist etching mask, the conductive metal layer is selectively etched, and the gate lines/gate electrodes/gate terminals
42
b/
42
a/
42
c
are left on the major surface of the transparent insulating plate
41
.
Subsequently, silicon nitride, amorphous silicon and heavily-doped n-type amorphous silicon are successively deposited over the entire surface of the resultant structure. The silicon nitride layer is 400 nanometers thick, and serves as the gate insulating layer
43
. The amorphous silicon layer and the heavily-doped n-type amorphous silicon layer are 300 nanometers thick and 50 nanometers thick, respectively. A photo-resist etching mask (not shown) is patterned on the heavily-doped n-type amorphous silicon layer by using the photo-lithographic techniques, and the amorphous silicon layer and the heavily-doped n-type amorphous silicon layer are selectively etched. Upon completion of the etching, the amorphous silicon layer is patterned into the semiconductor layer
44
, and the heavily-doped n-type amorphous silicon layer is laminated on the semiconductor layer
44
.
Subsequently, conductive metal such as Mo or Cr is deposited to 100 nanometers to 200 nanometers thick over the entire surface of the resultant structure by using the sputtering technique, and a photo-resist etching mask (not shown) is patterned on the conductive metal layer by using the photo-lithographic techniques. Using the photo-resist etching mask, the conductive metal layer is selectively etched so as to form the source lines/source electrodes/drain electrodes/data terminals
46
b
/
46
a
/
47
/
46
c
on the gate insulating layer
43
. The heavily-doped n-type amorphous silicon layer is partially overlapped with the source electrode
46
a
and the drain electrode
47
.
Using the source/drain electrodes
46
a
/
47
as an etching mask, the exposed portion of the heavily-doped n-type amorphous silicon layer is etched away, and the back channel region is exposed. The source electrode
46
a
and the drain electrode
47
are electrically connected through the ohmic layers
45
to the semiconductor layer
44
as shown in FIG.
5
A.
Subsequently, silicon nitride is deposited to 100 nanometers to 200 nanometers thick over the entire surface of the resultant structure by using a plasma-assisted chemical vapor deposition. The silicon nitride layer serves as the passivation layer
48
.
A photo-resist etching mask (not shown) is patterned on the passivation layer
48
. Using the photo-resist etching mask, the contact hole
51
, the contact hole for the data terminal
46
c
and the contact hole for the gate terminal
42
c
are formed in the passivation layer
48
. The resultant struct

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